Towards hierarchical cluster based cache coherence for large-scale network-on-chip

Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era

Volumn , Issue , 2009, Pages 119-122

  Zhang, Yuang ^a,b   Lu, Zhonghai ^b   Jantsch, Axel ^b   Li, Li ^a   Gao, Minglun ^a  

^a NANJING UNIVERSITY   (China)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Cache coherence; Hierarchical directory; Network cluster; Network on chip

Indexed keywords

CACHE COHERENCE; COMMUNICATION COST; DISTRIBUTED MEMORY ARCHITECTURE; HIERARCHICAL CLUSTERS; HIERARCHICAL DIRECTORY; HIERARCHICAL MEMORY; LARGE-SCALE NETWORK; MEMORY OVERHEADS; NETWORK CLUSTER; NETWORK-ON-CHIP;

INTEGRATED CONTROL; NANOSTRUCTURED MATERIALS;

ELECTRIC NETWORK TOPOLOGY;

EID: 67650364848     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DTIS.2009.4938037     Document Type: Conference Paper

References (15)

1. Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch, "The Nostrum backbone-a communication protocol stack for Networks on Chip", 17th International Conference on VLSI Design, 2004. Page(s):693 - 696
2. Axel Jantsch, Hannu Tenhunen, editors, "Networks on Chip", Kluwer Academic Publishers, 2003
3. John L.Hennessy, David A.Patterson, "Computer Architecture: A Quantitative Approach Fourth Edition", Morgan Kaufmann Publishers, 2007
4. Milo Tomasevic, Veljko Milutinovic, "A survey of hardware solutions for maintenance of cache coherence in shared memory multiprocessors", Proceeding of the Twenty-Sixth Hawaii International Conference on System Science, 1993, Volume i, 5-8 Jan 1993 Pages: 863-872 vol.1
5. John Hennessy, Mark Heinrich, Anoop Gupta, "Cache-coherent distributed shared memory: perspectives on its development and future challenges", Proceedings of the IEEE, Volume 87, Issue 3, March 1999 Pages: 418-429
6. David Chaiken, Craig Fields, Kiyoshi Kurihara, Anant Agarwal, "Directory-based cache coherence in large-scale multiprocessors", Computer, Volume 23, Issue 6, June 1990 Pages: 49-58 (Pubitemid 20737721)
7. Milo Tomasevic, Veljko Milutinovic, "Hardware approaches coherence in shared-memory multiprocessors" part 1, IEEE Micro, Volume 14, Issure 5, October 1994 Pages: 52-59
8. David E.Culler, Jaswinder Pal Singh, Anoop Gupta, "Parallel Computer Architecture: A Hardware/Software Approach", Morgan Kaufmann Publishers, 1999
9. Daniel Lenoski, James Laudon, Kourosh Garachorloo, Wolf-Dietrich Webbser, Anoop Gupta, John Hennessy, Mark Horowitz, and Monica S.Lam, "The Stanford Dash Multiprocessor", Computer, Volume 87, Issue 3, March 1992 pages: 418- 429
10. Deborah A.Wallach, "PHD: A Hierarchical Cache Coherent Protocol", master thesis, MIT, September 1992
11. Manuel E.Acacio, Jose Gonzalez,Jose M.Garcia, Jose Duato, "A Two- Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors", IEEE Transactions on parallel and distributed systems, Volume 16, No. 1, January 2005 (Pubitemid 40182042)
12. F. Petrot, A. Greiner, P. Gomez, "On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures", 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, 2006, Pages: 53-60 (Pubitemid 47271459)
13. Gustavo Girao, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva, "Cache Coherency Communicaton Cost in a NoC-based MPSoC Platform", Proceedings of the 20th annual conference on Integrated circuits and systems design, September 2007, Pages: 288 - 293
14. Noel Eisley, Li-Shiuan Peh, Li Shang, "In-Network cache coherence", The 39th Annual IEEE/ACM International Symposium on Microarchitecture 2006 (Pubitemid 351337007)
15. E. Bolotin, Z. Guz, I. Cidon, R. Ginosar, A. Kolodny, "The power of priority: NoC based distributed cache coherency", First International Symposium on Networks-on-Chip, May 2007, Pages: 117-126 (Pubitemid 350153584)