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Volumn , Issue , 2006, Pages 53-60

On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; INTEGRATED CIRCUITS; MULTIPROCESSING SYSTEMS;

EID: 34250827032     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.73     Document Type: Conference Paper
Times cited : (29)

References (22)
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    • P. Guerrier and A. Greiner. Architecture for on-chip packet-switched interconnections. In Proc of Design Automation and Test in Europe, pages 250-256, Paris, France, Mar. 2000.
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    • Guerrier, P.1    Greiner, A.2
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    • third edition, chapter 1.6, Quantitative Principles of Computer Design, Morgan Kaufmann Publisher, Inc
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    • (2003) Computer architecture, a quantitative approach , pp. 42-45
    • Hennessy, J.L.1    Patterson, D.A.2
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    • On-chip communication architecture for oc-768 network processors
    • Las Vegas, NV, June
    • F. Karim, A. Nguyen, S. Dey, and R. Rao. On-chip communication architecture for oc-768 network processors. In Proc. of the Design Automation Conf., pages 678-683, Las Vegas, NV, June 2001.
    • (2001) Proc. of the Design Automation Conf , pp. 678-683
    • Karim, F.1    Nguyen, A.2    Dey, S.3    Rao, R.4
  • 12
    • 0022141776 scopus 로고
    • Fat-trees: Universal networks for hardware efficient supercomputing
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    • C. E. Leiserson. Fat-trees: Universal networks for hardware efficient supercomputing. IEEE Trans. on Comp., C-34(10):892-901, Oct. 1985.
    • (1985) IEEE Trans. on Comp , vol.C-34 , Issue.10 , pp. 892-901
    • Leiserson, C.E.1
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    • 34547964151 scopus 로고    scopus 로고
    • Medea+ eda roamap 4th release, 2003
    • Medea+ eda roamap 4th release, 2003.
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    • 34547988070 scopus 로고    scopus 로고
    • Open Microprocessor systems Initiative, Apr.-May
    • Open Microprocessor systems Initiative. OMI 324: Pi-Bus, Apr.-May 1996.
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  • 18
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    • Lightweight implementation of the posix threads api for an on-chip mips multiprocessor with vci interconnect
    • A. A. Jerraya, S. Yoo, D. Verkest, and N. Wehn, editors, chapter 3, Kluwer Academic Publisher, Nov
    • F Pétrot, P. Gomez, and D. Hommais. Lightweight implementation of the posix threads api for an on-chip mips multiprocessor with vci interconnect. In A. A. Jerraya, S. Yoo, D. Verkest, and N. Wehn, editors, Embedded Software for SoC, part 1, chapter 3, pages 25-38. Kluwer Academic Publisher, Nov. 2003.
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    • On caches for a (rt) multiprocessor environment. Unpublished
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.