Device scaling of high performance MOSFET with metal gate high-K at 32nm technology node and beyond

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2008, Pages 309-312

  Wang, Xinlin ^a   Shahidi, Ghavam ^b   Oldiges, Phil ^a   Khare, Mukesh ^a  

^a IBM RESEARCH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Channel length scaling; Device scaling; High performance CMOS; Metal high k gate

Indexed keywords

32 NM TECHNOLOGY; BAND EDGE; CHANNEL LENGTH; CHANNEL LENGTH SCALING; CMOS TECHNOLOGY; DELAY CALCULATION; DEVICE CHARACTERISTICS; DEVICE SCALING; HIGH PERFORMANCE CMOS; HIGH-K GATE DIELECTRICS; METAL GATE; MOS-FET; POLYSILICON GATES; POTENTIAL BENEFITS; RING OSCILLATOR; TRANSISTOR PERFORMANCE;

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); METALS; OSCILLATORS (ELECTRONIC); POLYSILICON;

GATE DIELECTRICS;

EID: 67650360870     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2008.4648299     Document Type: Conference Paper

References (6)

1. J.W. Sleight, I. Lauer, O. Dokumaci, D. M. Fried, D. Guo, B. Haran, S. Narasimha, C. Sheraw, D. Singh, M. Steigerwalt, X. Wang, P. Oldiges, D. Sadana, C.Y. Sung, W. Haensch, and M. Khare, "Challenges and Opportunities for High Performance 32 nm CMOS Technology", IEDM Tech. Dig. 2006
2. P. M. Zeitzoff, "Proceedings of the Custom Integrated Circuits Conference", 2004, p. 233-240.
3. Y. Abe, T. Oishi, K. Shiozawa, Y. tokuda, and S. Saton," Simulation study on comparision between Metal gate and polysilicon gate for sub-quarter-micron MOSFET's", IEEE Elec. Dev. Lett., vol. 20, No. 12, p632-634. 1999.
4. E. Gusev et al., "Advanced Gate Stacks with Fully Silicided (FUSI) Gates and High-κ Dielectrics Enhanced Performance at Reduced Gate Leakage", IEDM Tech. Dig. 2004, p79-82.
5. X. Wang, A. Bryant, P. Oldiges, S. Narasimha, R. Dennard and W. Haensch, "Simulation Study on Channel Length Scaling of High Performance Partially Depleted Metal Gate and Poly Gate SOI MOSFETs"SISPAD 2006, p283-286.
6. E. M. Buturla, P. E. Cottrell, B. M. Grossman, and K. A. Salsburg, "Finite-element analysis of semiconductor device: the FIELDAY program," IBM J. Res. Develop., vol. 25, pp. 218,1981.