Simulation study on channel length scaling of high performance partially depleted metal gate and poly gate SOI MOSFETs

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2006, Pages 283-286

  Xinlin, Wang ^a   Bryant, Andres ^b   Oldiges, Phil ^a   Narasimha, Shreesh ^a   Dennard, Robert ^c   Haensch, Wilfried ^c  

^a IBM RESEARCH   (United States)

^b System and Technology Group   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Channel lengh scaling; High performance; Metal gate; MOSFET; Poly gate depletion; Short channel effect

Indexed keywords

CARRIER CONCENTRATION; COMPUTER SIMULATION; GATE DIELECTRICS; OPTIMIZATION; TRANSISTORS;

CHANNEL LENGH SCALING; HIGH PERFORMANCE; POLY GATE DEPLETION;

MOSFET DEVICES;

EID: 42549139818     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2006.282891     Document Type: Conference Paper

References (8)

1. P. M. Zeitzoff, "MOSFET scaling trends and challenges through the end of the roadmap", Proceedings of the Custom Integrated Circuits Conference, p. 233-240, 2004.
2. E. Gusev, et al."Advanced gate stacks with fully silicided (FUSI) fates and high-κ dielectrics: Enhanced performance at reduced gate leakage" IEDM Tech. Dig. 2004, p79-82.
3. Y. Abe, T. Oishi, K. Shiozawa, Y. tokuda, and S. Satoh.," Simulation study on comparision between Metal gate and polysilicon gate for sub-quarter-micron MOSFET's", IEEE Elec. Dev. Lett., vol. 20, No. 12, p632-634. 1999.
4. A. Kumar and R. Dennard, "Carrier Confinement in UTSOI Devices: Impact of Metal Gate Work Function" unpublished.
5. E. M. Buturla, P. E. Cottrell, B. M. Grossman, and K. A. Salsburg, "Finite-element analysis of semiconductor device: the FIELDAY program," IBM J. Res. Develop., vol. 25, pp. 218, 1981
6. MeiKei Ieong, Ronald Logan, and James Slinkman, "Efficient quantum correction for multi-dimensional CMOS simulations", Proc. SISPAD, p. 129, 1998.
7. P. Ranade, T. Ghani, K. Kuhn, K. Mistry, S. Pae, L. Shifren, M. Stettler, K. Tone, S. tyagi and M. Bohr, "High performance 35nm Lgate CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2nm gate oxide", IEDM Tech. Dig., p. 227-230, 2005.
8. S. Su. et al. "45-nm node NiSi FUSI on nitrided oxide bulk CMOS fabricated by a novel integration process", IEDM Tech. Dig., p. 231-234, 2005.