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Volumn , Issue , 2008, Pages 69-72
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Level shifts and gate interfaces as vital ingredients in modeling of charge trapping
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Author keywords
[No Author keywords available]
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Indexed keywords
CHARGE STATE;
DETAILED MODELING;
FIRST-PRINCIPLES CALCULATION;
GATE CONTACT;
GATE INTERFACE;
GENERAL DESCRIPTION;
LEVEL SHIFT;
NANO METER RANGE;
RIGOROUS MODEL;
TRAP LEVELS;
DIELECTRIC MATERIALS;
GATE DIELECTRICS;
GATES (TRANSISTOR);
SEMICONDUCTOR DEVICE MANUFACTURE;
SEMICONDUCTOR DEVICE MODELS;
CHARGE TRAPPING;
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EID: 67650348357
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/SISPAD.2008.4648239 Document Type: Conference Paper |
Times cited : (3)
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References (9)
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