A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards

2008 IEEE International SOC Conference, SOCC

Volumn , Issue , 2008, Pages 367-370

  Sun, Yang ^a   Cavallaro, Joseph R ^a  

^a Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

4G WIRELESS; AREA EFFICIENT; BELIEF PROPAGATION ALGORITHM; BELIEF PROPAGATION DECODING ALGORITHMS; BEYOND 3G; CLOCK FREQUENCY; CMOS TECHNOLOGY; DATA PATHS; EFFICIENT SYSTEMS; LDPC CODES; LDPC DECODER; LOW POWER; METAL LAYER; MIN-SUM ALGORITHM; PARALLEL DECODING; PEAK POWER; POWER CONSUMPTION; POWER SAVINGS; RE-CONFIGURABLE; SOFT-INPUT SOFT-OUTPUT DECODERS; WIRELESS STANDARDS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BACKPROPAGATION ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; PARALLEL ALGORITHMS; PROGRAMMABLE LOGIC CONTROLLERS; STANDARDS;

DECODING;

EID: 67650261339     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2008.4641546     Document Type: Conference Paper

References (10)

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