New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Volumn , Issue , 2009, Pages 459-464

  Bong, Ji Hye ^a   Kwon, Yong Jin ^a   Min, Kyeong Sik ^a,b   Kang, Sung Mo ^b  

^a Kookmin University   (South Korea)

^b University of California   (United States)

Author keywords

Leakage current; Low leakage SRAM; Lowpower SRAM; Oxide tunneling leakage; SRAM

Indexed keywords

65-NM DEVICES; CONVENTIONAL CIRCUITS; DELAY OVERHEADS; DRIVING SCHEMES; LOW-LEAKAGE SRAM; LOWPOWER SRAM; POWER CONSUMPTION; POWER SAVINGS; READ OPERATION; SRAM; STATIC AND DYNAMIC; SUBTHRESHOLD; SWING VOLTAGE; SWITCHING POWER; TUNNELING LEAKAGE; VOLTAGE STRESS; WRITE OPERATIONS;

ELECTRIC POWER UTILIZATION; STATIC RANDOM ACCESS STORAGE;

TUNNELING (EXCAVATION);

EID: 67649669259     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810338     Document Type: Conference Paper

References (8)

1. International technology roadmap for semiconductors, 2006.
2. http://www.eas.asu.edu/~ptm & W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45nm design exploration," IEEE International Symposium on Quality Electronic Design, pp. 585-590, 2006.
3. D. Lee et al., "Comparative study on leakage current of power-gated SRAMs for 65-nm, 45-nm, and 32-nm technology nodes," Journal of Computers, vol. 3, no. 3, pp. 39-47, March 2008.
4. H. Kawaguchi, Y. Iataka, and T. Sakurai, "Dynamic leakage cut-off scheme for low-voltage SRAM's," IEEE Technical digest of Symposium on VLSI circuits, pp. 140-141, June 1998.
5. A. Agarwal, H. Li, and K. Roy, "A single Vt lowleakage gated-ground cache for deep submicron," IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 319-328, Feb. 2003.
6. K. Kanda, T. Miyazaki, K. Min, H. Kawaguchi, and T. Sakurai, "Two orders of magnitude reduction of low voltage SRAM's by row-by-row dynamic VDD control (RDDV) scheme," Proceedings of IEEE International ASIC/SOC Conference, pp. 381-385, Rochester in USA, Sep. 2002.
7. T. Enomoto, Y. Oka, and H. Shikano, "A selfcontrollable voltage level (SVL) circuit and its lowpower high-speed CMOS circuit applications," IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1220-1226, July 2003.
8. K. Min et al., "Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders ofmagnitude leakage current reduction of sub-1-V-VDD SRAM's," IEICE Trans. Electron., vol. E87-C, no. 7, pp. 1208-1213, July 2004.