Estimation and optimization of reliability of noisy digital circuits

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Volumn , Issue , 2009, Pages 213-219

  Sivaswamy, Satish ^a   Bazargan, Kia ^a   Riedel, Marc ^a  

^a University of Minnesota   (United States)

Author keywords

And Fault Tolerance; Automatic Synthesis; Optimization; Reliability; Testing

Indexed keywords

AND FAULT-TOLERANCE; AUTOMATIC SYNTHESIS; CIRCUIT TRANSFORMATION; COMPUTATIONALLY EFFICIENT; CRITICAL CHALLENGES; ESTIMATION AND OPTIMIZATION; EXACT ANALYSIS; HYBRID APPROACH; HYBRID METHOD; MONTE CARLO SIMULATION; NOISY DIGITAL CIRCUITS; OPTIMIZATION FRAMEWORK; PROBABILISTIC MEASURES;

DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; FAULT TOLERANCE; MONTE CARLO METHODS; OPTIMIZATION; RELIABILITY ANALYSIS;

QUALITY ASSURANCE;

EID: 67649657520     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810296     Document Type: Conference Paper

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