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Volumn , Issue , 2009, Pages 241-247

An efficient approach to SiP design integration

Author keywords

Optimization; System in Package (SiP)

Indexed keywords

COST CONSTRAINTS; DEFECT LEVELS; DESIGN METHODOLOGY; DEVELOPMENT COSTS; HIGH COSTS; MINIMAL COST; POWER CONSUMPTION; QUALITY CONSTRAINTS; SIP DESIGN; SOLUTION SPACE; SYSTEM-IN-PACKAGE; SYSTEM-IN-PACKAGE (SIP); SYSTEM-ON-A-CHIP DESIGNS; TEST COVERAGE; TIME-TO-MARKET;

EID: 67649644208     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810301     Document Type: Conference Paper
Times cited : (2)

References (10)
  • 6
    • 33845593911 scopus 로고    scopus 로고
    • Exploring the Challenges in Creating a High-quality Mainstream Design Solution for System-in-Package (SiP) Design
    • B. McCaffrey, "Exploring the Challenges in Creating a High-quality Mainstream Design Solution for System-in-Package (SiP) Design," in Proc. International Symposium Quality of Electronic Design, pp. 556-561, 2005.
    • (2005) Proc. International Symposium Quality of Electronic Design , pp. 556-561
    • McCaffrey, B.1
  • 7
    • 0025798634 scopus 로고
    • BIST and Interconnect Testing with Boundary Scan
    • Apr
    • A. A. Setty, H. L. Martin, "BIST and Interconnect Testing with Boundary Scan," in Proc. Southeastcon, vol. 1, pp. 12-15, Apr, 1991.
    • (1991) Proc. Southeastcon , vol.1 , pp. 12-15
    • Setty, A.A.1    Martin, H.L.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.