-
1
-
-
3242671509
-
-
T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johson, C. Kenyon, S. Thompson, and M. Bohr, A 90 nm high manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors, in IEDM Tech. Dig., 2003, pp. 11.6.1-11.6.3.
-
T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johson, C. Kenyon, S. Thompson, and M. Bohr, "A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors," in IEDM Tech. Dig., 2003, pp. 11.6.1-11.6.3.
-
-
-
-
2
-
-
0031191310
-
Elementary scattering theory of the Si MOSFET
-
Jul
-
M. Lundstrom, "Elementary scattering theory of the Si MOSFET," IEEE Electron Device Lett., vol. 18, no. 7, pp. 361-363, Jul. 1997.
-
(1997)
IEEE Electron Device Lett
, vol.18
, Issue.7
, pp. 361-363
-
-
Lundstrom, M.1
-
3
-
-
46049110549
-
High mobility materials and novel device structures for high performance nanoscale MOSFETs
-
K. C. Saraswat, C. O. Chui, T. Krishnamohan, and A. Pethe, "High mobility materials and novel device structures for high performance nanoscale MOSFETs," in IEDM Tech. Dig., 2006, pp. 659-662.
-
(2006)
IEDM Tech. Dig
, pp. 659-662
-
-
Saraswat, K.C.1
Chui, C.O.2
Krishnamohan, T.3
Pethe, A.4
-
4
-
-
33750533177
-
Integration of germanium-on-insulator and silicon MOSFETs on a silicon substrate
-
Nov
-
J. Feng, Y. Liu, P. B. Griffin, and J. D. Plummer, "Integration of germanium-on-insulator and silicon MOSFETs on a silicon substrate," IEEE Electron Device Lett., vol. 27, no. 11, pp. 911-913, Nov. 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.11
, pp. 911-913
-
-
Feng, J.1
Liu, Y.2
Griffin, P.B.3
Plummer, J.D.4
-
5
-
-
50349102620
-
105 nm gate length pMOSFETs with high-k metal gate fabricated in a Si process line on 200 nm GeOI wafers
-
Sep
-
C. Le Royer, L. Clavelier, C. Tabone, K. Romanjek, C. Deguet, L. Sanchez, J.-M. Hartmann, M.-C. Roure, H. Grampeix, S. Soliveres, G. Le Carval, R. Truche, A. Pouydebasque, M. Vinet, and S. Deleonibus, "105 nm gate length pMOSFETs with high-k metal gate fabricated in a Si process line on 200 nm GeOI wafers," Solid State Electron., vol. 52, no. 9, pp. 1285-1290, Sep. 2008.
-
(2008)
Solid State Electron
, vol.52
, Issue.9
, pp. 1285-1290
-
-
Le Royer, C.1
Clavelier, L.2
Tabone, C.3
Romanjek, K.4
Deguet, C.5
Sanchez, L.6
Hartmann, J.-M.7
Roure, M.-C.8
Grampeix, H.9
Soliveres, S.10
Le Carval, G.11
Truche, R.12
Pouydebasque, A.13
Vinet, M.14
Deleonibus, S.15
-
6
-
-
58049121341
-
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate
-
K. Romanjek, L. Hutin, C. Le Royer, A. Pouydebasque, M.-A. Jaud, C. Tabone, E. Augendre, L. Sanchez, J.-M. Hartmann, H. Grampeix, V. Mazzocchi, S. Soliveres, R. Truche, L. Clavelier, P. Scheiblin, X. Carros, G. Reimbold, M. Vinet, F. Boulanger, and S. Deleonibus, "High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate," in ESSDERC, 2008, pp. 75-87.
-
(2008)
ESSDERC
, pp. 75-87
-
-
Romanjek, K.1
Hutin, L.2
Le Royer, C.3
Pouydebasque, A.4
Jaud, M.-A.5
Tabone, C.6
Augendre, E.7
Sanchez, L.8
Hartmann, J.-M.9
Grampeix, H.10
Mazzocchi, V.11
Soliveres, S.12
Truche, R.13
Clavelier, L.14
Scheiblin, P.15
Carros, X.16
Reimbold, G.17
Vinet, M.18
Boulanger, F.19
Deleonibus, S.20
more..
-
7
-
-
46149119210
-
High performance Ge pMOS devices using a Si-compatible process flow
-
P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans, L.-A. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, "High performance Ge pMOS devices using a Si-compatible process flow," in IEDM Tech. Dig., 2006, pp. 1-4.
-
(2006)
IEDM Tech. Dig
, pp. 1-4
-
-
Zimmerman, P.1
Nicholas, G.2
De Jaeger, B.3
Kaczer, B.4
Stesmans, A.5
Ragnarsson, L.-A.6
Brunco, D.P.7
Leys, F.E.8
Caymax, M.9
Winderickx, G.10
Opsomer, K.11
Meuris, M.12
Heyns, M.M.13
-
8
-
-
64549141495
-
Record Ion/Ioff performance for 65 nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
-
J. Mitard, B. De. Jaeger, F. E. Leys, G. Hellings, K. Martens, G. Eneman, D. P. Brunco, R. Loo, J. C. Lin, D. Shamiryan, T. Vandeweyer, G. Winderickx, E. Vrancken, C. H. Yu, K. De Meyer, M. Caymax, L. Pantisano, M. Meuris, and M. M. Heyns, "Record Ion/Ioff performance for 65 nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability," in IEDM Tech. Dig., 2008, pp. 873-876.
-
(2008)
IEDM Tech. Dig
, pp. 873-876
-
-
Mitard, J.1
Jaeger, B.D.2
Leys, F.E.3
Hellings, G.4
Martens, K.5
Eneman, G.6
Brunco, D.P.7
Loo, R.8
Lin, J.C.9
Shamiryan, D.10
Vandeweyer, T.11
Winderickx, G.12
Vrancken, E.13
Yu, C.H.14
De Meyer, K.15
Caymax, M.16
Pantisano, L.17
Meuris, M.18
Heyns, M.M.19
-
9
-
-
0842266606
-
2 gate dielectric and TaN gate electrode
-
2 gate dielectric and TaN gate electrode," in IEDM Tech. Dig., 2003, pp. 433-435.
-
(2003)
IEDM Tech. Dig
, pp. 433-435
-
-
Ritenour, A.1
Yu, S.2
Lee, M.L.3
Lu, N.4
Bai, W.5
Pitera, A.6
Fitzgerald, E.A.7
Kwong, D.L.8
Antoniadis, D.A.9
-
10
-
-
0001398969
-
High-quality Ge epilayers on Si with low threading-dislocation densities
-
Nov
-
H. Luan, D. R. Lim, K. K. Lee, K. M. Chen, J. G. Sandland, K. Wada, and L. C. Kimerling, "High-quality Ge epilayers on Si with low threading-dislocation densities," Appl. Phys. Lett., vol. 75, no. 19, p. 2909, Nov. 1999.
-
(1999)
Appl. Phys. Lett
, vol.75
, Issue.19
, pp. 2909
-
-
Luan, H.1
Lim, D.R.2
Lee, K.K.3
Chen, K.M.4
Sandland, J.G.5
Wada, K.6
Kimerling, L.C.7
-
11
-
-
8344282844
-
Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality
-
Oct. 4
-
A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, "Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality," Appl. Phys. Lett.,, vol. 85, no. 14, pp. 2815-2817, Oct. 4, 2004.
-
(2004)
Appl. Phys. Lett
, vol.85
, Issue.14
, pp. 2815-2817
-
-
Nayfeh, A.1
Chui, C.O.2
Saraswat, K.C.3
Yonehara, T.4
-
12
-
-
0033097369
-
Fabrication of high-mobility Ge p-channel MOSFETs on Si substrate
-
Mar
-
D. Reinking, M. Kammler, N. Hoffmann, M. Horn-Von Hoegen, and K. R. Hofmann, "Fabrication of high-mobility Ge p-channel MOSFETs on Si substrate," Electron. Lett., vol. 35, no. 6, pp. 503-504, Mar. 1999.
-
(1999)
Electron. Lett
, vol.35
, Issue.6
, pp. 503-504
-
-
Reinking, D.1
Kammler, M.2
Hoffmann, N.3
Horn-Von Hoegen, M.4
Hofmann, K.R.5
-
13
-
-
0001576164
-
High quality Ge on Si by epitaxial necking
-
Jun
-
T. A. Langdo, C. W. Leitz, M. T. Currie, E. A. Fitzgerald, A. Lochtefeld, and D. A. Antoniadis, "High quality Ge on Si by epitaxial necking," Appl. Phys. Lett., vol. 76, no. 25, p. 3700, Jun. 2000.
-
(2000)
Appl. Phys. Lett
, vol.76
, Issue.25
, pp. 3700
-
-
Langdo, T.A.1
Leitz, C.W.2
Currie, M.T.3
Fitzgerald, E.A.4
Lochtefeld, A.5
Antoniadis, D.A.6
-
14
-
-
33846982216
-
Defect reduction of selective Ge epitaxy in trenches on Si(001) substrates using aspect ratio trapping
-
Jan
-
J.-S. Park, J. Bai, M. Curtin, B. Adekore, M. Carroll, and A. Lochtefeld, "Defect reduction of selective Ge epitaxy in trenches on Si(001) substrates using aspect ratio trapping," Appl. Phys. Lett. vol. 90, no. 5, p. 052 113, Jan. 2007.
-
(2007)
Appl. Phys. Lett
, vol.90
, Issue.5
, pp. 052-113
-
-
Park, J.-S.1
Bai, J.2
Curtin, M.3
Adekore, B.4
Carroll, M.5
Lochtefeld, A.6
-
15
-
-
64849086849
-
Low Dit optimized interfacial layer using high-density plasma oxidation and nitridation in germanium high-k gate stack
-
G. Thareja, M. Kobayashi, Y. Oshima, J. McVittie, P. Griffin, and Y. Nishi, "Low Dit optimized interfacial layer using high-density plasma oxidation and nitridation in germanium high-k gate stack," in IEEE 66th Device Res. Conf., 2008, pp. 87-88.
-
(2008)
IEEE 66th Device Res. Conf
, pp. 87-88
-
-
Thareja, G.1
Kobayashi, M.2
Oshima, Y.3
McVittie, J.4
Griffin, P.5
Nishi, Y.6
-
16
-
-
0036923998
-
A sub 400 °C germanium MOSFET technology with high-k dielectric and metal gate
-
C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntryre, and K. C. Saraswat, "A sub 400 °C germanium MOSFET technology with high-k dielectric and metal gate," in IEDM Tech. Dig., 2002, pp. 437-440.
-
(2002)
IEDM Tech. Dig
, pp. 437-440
-
-
Chui, C.O.1
Kim, H.2
Chi, D.3
Triplett, B.B.4
McIntryre, P.C.5
Saraswat, K.C.6
-
17
-
-
0038781387
-
Electrical characterization of germanium p-channel MOSFETs
-
Apr
-
H. Shang, H. Okorn-Schimdt, J. Ott, P. Kozlowski, S. Steen, E. C. Jones, H.-S. P. Wong, and W. Hanesch, "Electrical characterization of germanium p-channel MOSFETs," IEEE Electron Device Lett., vol. 24, no. 4, pp. 242-244, Apr. 2003.
-
(2003)
IEEE Electron Device Lett
, vol.24
, Issue.4
, pp. 242-244
-
-
Shang, H.1
Okorn-Schimdt, H.2
Ott, J.3
Kozlowski, P.4
Steen, S.5
Jones, E.C.6
Wong, H.-S.P.7
Hanesch, W.8
-
18
-
-
0028747841
-
On the universality of inversion layer mobility in Si MOSFETs: Part I - Effects of substrate impurity concentration
-
Dec
-
S. I. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFETs: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.12
, pp. 2357-2362
-
-
Takagi, S.I.1
Toriumi, A.2
Iwase, M.3
Tango, H.4
-
19
-
-
33847710271
-
Dramatic improvement of Ge p-MOSFET characteristics realized by amorphous Zr-silicate/Ge gate stack with excellent structural stability through process temperatures
-
Y. Kamata, Y. Kamimuta, T. Ino, R. Iijima, M. Koyama, and A. Nishiyama, "Dramatic improvement of Ge p-MOSFET characteristics realized by amorphous Zr-silicate/Ge gate stack with excellent structural stability through process temperatures," in IEDM Tech. Dig., 2005, pp. 429-432.
-
(2005)
IEDM Tech. Dig
, pp. 429-432
-
-
Kamata, Y.1
Kamimuta, Y.2
Ino, T.3
Iijima, R.4
Koyama, M.5
Nishiyama, A.6
-
20
-
-
19044372579
-
Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si
-
May
-
A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, "Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si," IEEE Electron Device Lett., vol. 26, no. 5, pp. 311-313, May 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, Issue.5
, pp. 311-313
-
-
Nayfeh, A.1
Chui, C.O.2
Yonehara, T.3
Saraswat, K.C.4
-
21
-
-
50249091022
-
Interface-engineered Ge (100) and (111), N- and P-FETs with high mobility
-
D. Kuzum, A. J. Pethe, T. Krishnamohan, Y. Oshima, Y. Sun, J. P. McVittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, "Interface-engineered Ge (100) and (111), N- and P-FETs with high mobility," in IEDM Tech. Dig., 2007, pp. 723-725.
-
(2007)
IEDM Tech. Dig
, pp. 723-725
-
-
Kuzum, D.1
Pethe, A.J.2
Krishnamohan, T.3
Oshima, Y.4
Sun, Y.5
McVittie, J.P.6
Pianetta, P.A.7
McIntyre, P.C.8
Saraswat, K.C.9
-
22
-
-
64549106030
-
2 interfacial layers
-
2 interfacial layers," in IEDM Tech. Dig., 2008, p. 877.
-
(2008)
IEDM Tech. Dig
, pp. 877
-
-
Nakakita, Y.1
Nakane, R.2
Sasada, T.3
Matsubara, H.4
Takenaka, M.5
Takagi, S.6
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