A manufacturing cost model for 3-D monolithic memory integrated circuits

IEEE Transactions on Semiconductor Manufacturing

Volumn 22, Issue 2, 2009, Pages 268-275

  Walker, Andrew J ^a  

^a Schiltron Corporation   (United States)

Author keywords

3 D; memory; nonvolatile (NV); Yield

Indexed keywords

3-D; COST MODELS; MAIN PARAMETERS; MANUFACTURING COST; MEMORY; MEMORY CAPACITY; MEMORY CELL; MONOLITHIC CHIP; NAND FLASH; NONVOLATILE (NV); NONVOLATILE MEMORY CELLS; PROCESS INTEGRATION; PROCESS STEPS; SILICON SUBSTRATES; SINGLE CHIPS; TOTAL COSTS; YIELD;

COSTS; FLASH MEMORY; MONOLITHIC INTEGRATED CIRCUITS; PARAMETER ESTIMATION; SEMICONDUCTOR STORAGE;

THREE DIMENSIONAL;

EID: 67649246871     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2009.2017643     Document Type: Article

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