Derivation and implication of a novel DRAM bit cost model

IEEE Transactions on Semiconductor Manufacturing

Volumn 15, Issue 2, 2002, Pages 279-284

  Nakatsuka, Haruo ^a,b,c  

^a IEEE   (Japan)

^b TOSHIBA CORPORATION   (Japan)

^c Applied Materials Japan Inc   (Japan)

Author keywords

Critical area; Defect density; Defect size distribution; DRAM cost trend; Technology roadmap; Yield model

Indexed keywords

DEFECT DENSITY;

COST EFFECTIVENESS; DEFECTS; LSI CIRCUITS; MATHEMATICAL MODELS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036565013     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.999606     Document Type: Conference Paper

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