A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1074-1077

  Wey, I Chyn ^a   Chang, Lung Hao ^a   Chen, You Gang ^a   Chang, Shih Hung ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ART DESIGN; CLOCK FREQUENCY; DYNAMIC CONTROLS; HIGH-SPEED; ON CHIPS; ON-CHIP SERIAL COMMUNICATIONS; RELIABLE CONTROL; RING OSCILLATOR; SCALABLE DESIGN; SERIAL COMMUNICATIONS; SERIAL TRANSMISSION; SOC APPLICATION; TIMING CONSTRAINTS; TRANSMISSION BANDWIDTH;

PHASE INTERFACES; PROGRAMMABLE LOGIC CONTROLLERS; SHIFT REGISTERS; TELECOMMUNICATION SYSTEMS; TIMING CIRCUITS;

DESIGN;

EID: 67649088653     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464778     Document Type: Conference Paper

References (7)

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7. J. S. Wang, et al, " Design of a 3-V 300MHz Low-Power 8-b X 8-b Pipelined Multipliers Using Pulse-Triggerd TSPC Flip-Flops" IEEE JSSC, vol 35, pp. 583-592, April 2000.