Characterization and modeling of subfemtofarad nanowire capacitance using the CBCM technique

IEEE Electron Device Letters

Volumn 30, Issue 5, 2009, Pages 526-528

  Zhao, Hui ^a,b   Kim, Raseong ^c   Paul, Abhijeet ^c   Luisier, Mathieu ^c   Klimeck, Gerhard ^c   Ma, Fa Jun ^a,b   Rustagi, Subhash C ^a   Samudra, Ganesh S ^b   Singh, Naveb ^a   Lo, Guo Qiang ^a   Kwong, Dim Lee ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c Purdue University   (United States)

Author keywords

Charge based capacitance measurement (CBCM); Nanowire MOSFETs; Self consistent C V modeling; Subfemtofarad capacitance measurement

Indexed keywords

CHARGE-BASED CAPACITANCE MEASUREMENT (CBCM); CHARGE-BASED CAPACITANCE MEASUREMENTS; DEVICE SIMULATIONS; EXPERIMENTAL CHARACTERIZATION; GATE CAPACITANCE; INTRINSIC GATE CAPACITANCE; MEASUREMENT RESULTS; NANOSCALE DEVICE; NANOWIRE MOSFETS; NANOWIRE TRANSISTORS; SELF-CONSISTENT C-V MODELING; SEM AND TEM; SINGLE-CHANNEL; SUBFEMTOFARAD-CAPACITANCE MEASUREMENT; TIGHT BINDING;

CAPACITANCE; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; NANOWIRES; THREE DIMENSIONAL;

CAPACITANCE MEASUREMENT;

EID: 67349280630     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2015588     Document Type: Article

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