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Volumn 41, Issue 1, 2009, Pages 233-244

Reconfigurable logic blocks based on a chaotic Chua circuit

Author keywords

[No Author keywords available]

Indexed keywords

CHAOTIC SYSTEMS; LOGIC CIRCUITS; TIMING CIRCUITS;

EID: 67349247407     PISSN: 09600779     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.chaos.2007.11.030     Document Type: Article
Times cited : (15)

References (14)
  • 1
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    • Computing with distributed chaos
    • Sinha S., and Ditto W.L. Computing with distributed chaos. Phys Rev E 60 (1999) 363-377
    • (1999) Phys Rev E , vol.60 , pp. 363-377
    • Sinha, S.1    Ditto, W.L.2
  • 2
    • 37649030639 scopus 로고    scopus 로고
    • Flexible parallel implementation of logic gates using chaotic elements
    • Sinha S., Munakata T., and Ditto W.L. Flexible parallel implementation of logic gates using chaotic elements. Phys Rev E 65 1-9 (2002) 036216
    • (2002) Phys Rev E , vol.65 , Issue.1-9 , pp. 036216
    • Sinha, S.1    Munakata, T.2    Ditto, W.L.3
  • 4
    • 0242508464 scopus 로고    scopus 로고
    • Implementation of NOR gate by a chaotic Chua's circuit
    • Murali K., Sinha S., and Ditto W.L. Implementation of NOR gate by a chaotic Chua's circuit. Int J Bifurcat Chaos (Lett.) 13 (2003) 2669-2672
    • (2003) Int J Bifurcat Chaos (Lett.) , vol.13 , pp. 2669-2672
    • Murali, K.1    Sinha, S.2    Ditto, W.L.3
  • 5
    • 17144383290 scopus 로고    scopus 로고
    • Realization of the fundamental NOR gate using a chaotic circuit
    • Murali K., Sinha S., and Ditto W.L. Realization of the fundamental NOR gate using a chaotic circuit. Phys Rev E 68 1-5 (2003) 016205
    • (2003) Phys Rev E , vol.68 , Issue.1-5 , pp. 016205
    • Murali, K.1    Sinha, S.2    Ditto, W.L.3
  • 6
    • 15744396078 scopus 로고    scopus 로고
    • Construction of a reconfigurable dynamic logic cell
    • Murali K., Sinha S., and Ditto W.L. Construction of a reconfigurable dynamic logic cell. Pramana-J Phys 64 3 (2005) 433-441
    • (2005) Pramana-J Phys , vol.64 , Issue.3 , pp. 433-441
    • Murali, K.1    Sinha, S.2    Ditto, W.L.3
  • 7
    • 33747477901 scopus 로고    scopus 로고
    • Chaos-based SR flip-flop via Chua's circuit
    • Cafagna D., and Grassi G. Chaos-based SR flip-flop via Chua's circuit. Int J Bifurcat Chaos 16 (2006) 1521-1526
    • (2006) Int J Bifurcat Chaos , vol.16 , pp. 1521-1526
    • Cafagna, D.1    Grassi, G.2
  • 8
    • 0031169872 scopus 로고    scopus 로고
    • Hierarchical interconnection structures for field programmable gate arrays
    • Lai Y., and Wang P. Hierarchical interconnection structures for field programmable gate arrays. IEEE Trans VLSI Syst 5 2 (1997) 186-196
    • (1997) IEEE Trans VLSI Syst , vol.5 , Issue.2 , pp. 186-196
    • Lai, Y.1    Wang, P.2
  • 9
    • 84856043672 scopus 로고
    • A mathematical theory of communication
    • Shannon C.E. A mathematical theory of communication. The Bell Syst Tech J 27 (1948)
    • (1948) The Bell Syst Tech J , vol.27
    • Shannon, C.E.1
  • 12
    • 0038672149 scopus 로고    scopus 로고
    • Review of chaos communication by feedback control of symbolic dynamics
    • Bollt E. Review of chaos communication by feedback control of symbolic dynamics. IJBC 13 2 (2003) 269-285
    • (2003) IJBC , vol.13 , Issue.2 , pp. 269-285
    • Bollt, E.1
  • 13
    • 0027681383 scopus 로고
    • Three steps to chaos-part two: a Chua circuit primer
    • Kennedy M.P. Three steps to chaos-part two: a Chua circuit primer. IEEE Trans Circuit Syst 40 10 (1993)
    • (1993) IEEE Trans Circuit Syst , vol.40 , Issue.10
    • Kennedy, M.P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.