A SIMD optimization framework for retargetable compilers

Transactions on Architecture and Code Optimization

Volumn 6, Issue 1, 2009, Pages

  Hohenauer, Manuel ^a   Engel, Felix ^a   Leupers, Rainer ^a   Ascheid, Gerd ^a   Meyr, Heinrich ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

ASIP; Retargetable compilers; SIMD; Subword parallelism; Vectorization

Indexed keywords

ASIP; RETARGETABLE COMPILERS; SIMD; SUBWORD PARALLELISM; VECTORIZATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; OPTIMIZATION; TARGETS;

PROGRAM COMPILERS;

EID: 67149109696     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1509864.1509866     Document Type: Article

References (42)

1. ASSOCIATED COMPUTER EXPERTS (ACE). The COSY compiler development system. http://www. ace.nl.
2. ADVANCED RISC MACHINES LTD. The ARM11 processor. http://www.arm.com.
3. ALLEN, J. R., KENNEDY, C. P., AND WARREN, J. 1983. Conversion of control dependence to data dependence. In Proceedings of the 10th ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages (POPL'83). ACM, New York.
4. ALLEN, R. AND KENNEDY, K. 1987. Automatic translation of FORTRAN programs to vector form. ACM Trans. Program. Lang. Syst. 9, 4, 491-542. (Pubitemid 18531687)
5. CHEONG, G. AND LAM, M. S. 1997. An optimizer for multimedia instruction sets. In Proceedings of the 2nd SUIF Compiler Workshop. Stanford University, CA.
6. COWARE INC. Processor Designer. http://www.coware.com.
7. EICHENBERGER, A. E., WU, P., AND O'BRIEN, K. 2004. Vectorization for SIMD architectures with alignment constraints. In Proceedings of the International Conference on Programming Language Design and Implementation (PLDI'04). ACM, New York, 82-93.
8. FISHER, J. A. 1999. Customized instruction-sets for embedded processors. In Proceedings of the Design Automation Conference (DAC'99). ACM, New York, 253-257.
9. FRANCHETTI, F., KRAL, S., LORENZ, J., AND UEBERHUBER, C. W. 2005. Efficient utilization of SIMD extensions. Proc. IEEE. 93, 2, 409-425.
10. FRASER, C. W., HANSON, D. R., AND PROEBSTING, T. A. 1992. Engineering a simple, efficient codegenerator generator. ACM Lett. Program. Lang. Syst. 1, 3, 213-226.
11. FRASER, C.W., HENRY, R. R., AND PROEBSTING, T. A. 1992. BURG: Fast optimal instruction selection and tree parsing. SIGPLAN Not. 27, 4, 68-76.
12. GLöCKLER, T., BITTERLICH, S., AND MEYR, H. 2000. ICORE: A low-power application specific instruction set processor for DVB-T acquisition and tracking. In Proceedings of the 13th Annual IEEE International ASIC/SOC Conference. IEEE, Los Alamitos, CA.
13. GNU COMPILER COLLECTION. Auto-vectorization in GCC. http://gcc.gnu.org/ projects/treessa/vectorization.html.
14. GRIES, M. AND KEUTZER, K. 2005. Building ASIPs: The Mescal Methodology. Springer-Verlag, Berlin, Germany.
15. HOFFMANN, A., KOGEL, T., AND MEYR, H. 2001. A framework for fast hardware-software cosimulation. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE'01). IEEE, Los Alamitos, CA.
16. HOFFMANN, A., MEYR, H., AND LEUPERS, R. 2002. Architecture Exploration for Embedded Processors with LISA. Kluwer Academic Publishers, The Netherlands
17. HOHENAUER, M., SCHARWAECHTER, H., KARURI, K., WAHLEN, O., KOGEL, T., LEUPERS, R., ASCHEID, G., MEYR, H., BRAUN, G., AND VAN SOMEREN, H. 2004. A methodology and tool suite for C compiler generation from ADL processor models. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE'04). IEEE, Los Alamitos, CA, 1276.
18. HOHENAUER, M., SCHUMACHER, C., LEUPERS, R., ASCHEID, G., MEYR, H., AND V. SOMEREN, H. 2006. Retargetable code optimization with SIMD instructions. In Proceedings of the International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS). ACM, New York, 148-153.
19. INTEL CORPORATION. Intel C compiler. http://www.intel.com.
20. KITAJIMA, A., ITOH, M., SATO, J., SHIOMI, A., TAKEUCHI, Y., AND IMAI, M. 2001. Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. In Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC'01). ACM, New York, 649-654.
21. KRALL, A. AND LELAIT, S. 2000. Compilation techniques for multimedia processors. Int. J. Parall. Prog. 28, 4, 347-361.
22. KUDRIAVTSEV, A. AND KOGGE, P. 2005. Generation of permutations for SIMD processors. In Proceedings of the International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05). ACM, New York, 147-156.
23. LARSEN, S. AND AMARASINGHE, S. 2000. Exploiting superword level parallelism with multimedia instruction-sets. In Proceedings of the International Conference on Programming Language Design and Implementation (PLDI'00). ACM, New York, 145-156. (Pubitemid 32394090)
24. LARSEN, S. W. E. AND AMARASINGHE, S. P. 2002. Increasing and detecting memory address congruence. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'02). IEEE, Los Alamitos, CA, 18-29.
25. LEUPERS, R. 2000a. Code Optimization Techniques for Embedded Processors. Kluwer Academic Publishers, The Netherlands.
26. LEUPERS, R. 2000b. Code selection for media processors with SIMD instructions. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'00). ACM, New York, 4-8.
27. LEUPERS, R. AND MARWEDEL, P. 2001. Retargetable Compiler Technology for Embedded Systems. Kluwer Academic Publishers, The Netherlands.
28. MISHRA, P., DUTT, N., AND NICOLAU, A. 2001. Functional abstraction driven design space exploration of heterogeneous programmable architectures. In Proceedings of the International Symposium on System Synthesis (ISSS'01). ACM, New York, 256-261. (Pubitemid 32951042)
29. MUCHNICK, S. S. 1997. Advanced Compiler Design & Implementation. Morgan Kaufmann Publishers, San Francisco, CA.
30. NUZMAN, D. AND HENDERSON, R. 2006. Multi-platform auto-vectorization. In Proceedings of the International Symposium on Code Generation and Optimization (CGO'06). IEEE, Los Alamitos, CA, 281-294.
31. NUZMAN, D., ROSEN, I., AND ZAKS, A. 2006. Auto-vectorization of interleaved data for SIMD. In Proceedings of the International Conference on Programming Language Design and Implementation (PLDI'06). ACM, New York, 132-143.
32. NXP Semiconductors. The TriMedia media processor. http://www.nxp.com.
33. ORAIOGLU, A. AND VEIDENBAUM, A. 2003. Application specific microprocessors (Guest Editors' Introduction). IEEE Des. Test Comput. 20.
34. POKAM, G., BIHAN, S., SIMONNET, J., AND BODIN, F. 2004. SWARP: A retargetable preprocessor for multimedia instructions. Concurr. Comput. Pract. Exper. 16, 2-3, 303-318.
35. PRYANISHNIKOV, I., KRALL, A., AND HORSPOOL, N. 2003. Pointer alignment analysis for processors with SIMD instructions. In Proceedings of the 5thWorkshop on Media and Streaming Processors. ACM, New York.
36. REN, G., WU, P., AND PADUA, D. 2003. A preliminary study on the vectorization of multimedia applications for multimedia extensions. In Proceedings of the 16th International Workshop of Languages and Compilers for Parallel Computing. Springer, Berlin, Germany.
37. REN, G., WU, P., AND PADUA, D. 2006. Optimizing data permutations for SIMD devices. In Proceedings of the International Conference on Programming Language Design and Implementation (PLDI'06). ACM, New York, 118-131.
38. RIZZOLO, N. AND PADUA, D. 2005. HiLO: high level optimization of FFTs. In Proccedings of the 18th International Conference on Languages and Compilers for High Performance Computing. Springer, Berlin, Germany, 238-252. (Pubitemid 41435891)
39. TENSILICA, INC. Xtensa C compiler. http://www.tensilica.com.
40. WOLFE, M. J. 1995. High Performance Compilers for Parallel Computing. Addison-Wesley Longman, Boston, MA.
41. WU, P., EICHENBERGER, A. E., AND WANG, A. 2005. Efficient SIMD code generation for runtime alignment and length conversion. In Proceedings of the International Symposium on Code Generation and Optimization (CGO'05). IEEE, Los Alamitos, CA, 153-164. (Pubitemid 43773801)
42. ZIVOJNOVIC, V., VELARDE, J., SCHLäGER, C., AND MEYR, H. 1994. DSPStone - a DSP-oriented benchmarking methodology. In Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT). IASTED, Calgary, Alberta.