Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 649-654

  Kitajima, A ^a   Itoh, M ^a   Sato, J ^b   Shiomi, A ^c   Takeuchi, Y ^a   Imai, M ^a  

^a OSAKA UNIVERSITY   (Japan)

^b TSURUOKA NATIONAL COLLEGE OF TECHNOLOGY   (Japan)

^c SHIZUOKA UNIVERSITY   (Japan)

Author keywords

Application specific processors; Costs; Embedded system; Hardware; Informatics; Pipeline processing; Process design; Reduced instruction set computing; Space exploration; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE; COSTS; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; HARDWARE; INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; PROCESS DESIGN; PROGRAM PROCESSORS; REDUCED INSTRUCTION SET COMPUTING; SPACE RESEARCH; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS;

APPLICATION SPECIFIC PROCESSORS; INFORMATICS; PIPELINE PROCESSING; SPACE EXPLORATIONS; SYSTEM ON A CHIP;

PIPELINE PROCESSING SYSTEMS;

EID: 84949799781     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913383     Document Type: Conference Paper

References (7)

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