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Volumn 7275, Issue , 2009, Pages

Developing DRC plus rules through 2D pattern extraction and clustering techniques

Author keywords

Classify; Design; Hotspot; Manufacturability; Pattern; Rule; Style; Variability

Indexed keywords

CLASSIFY; HOTSPOT; MANUFACTURABILITY; PATTERN; RULE; STYLE; VARIABILITY;

EID: 66749128679     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.814347     Document Type: Conference Paper
Times cited : (34)

References (10)
  • 1
    • 35148855049 scopus 로고    scopus 로고
    • DRC Plus: Augmenting standard DRC with pattern matching on 2D geometries
    • V. Dai, J. Yang, L. Capodieci, N. Rodriguez, "DRC Plus: augmenting standard DRC with pattern matching on 2D geometries," Proc. SPIE, Vol. 6521, 65210A (2007).
    • (2007) Proc. SPIE , vol.6521
    • Dai, V.1    Yang, J.2    Capodieci, L.3    Rodriguez, N.4
  • 2
    • 33745773693 scopus 로고    scopus 로고
    • L. Capodieci, From Optical Proximity Correction to Lithography-Driven Physical Design (1996-2006): 10 years of Resolution Enhancement Technology and the roadmap enablers for the next decade, Optical Microlithography XIX, edited by Donis G. Flagello, Proc. of SPIE 6154, 615401, (2006).
    • L. Capodieci, "From Optical Proximity Correction to Lithography-Driven Physical Design (1996-2006): 10 years of Resolution Enhancement Technology and the roadmap enablers for the next decade", Optical Microlithography XIX, edited by Donis G. Flagello, Proc. of SPIE Vol. 6154, 615401, (2006).
  • 3
    • 0038158890 scopus 로고    scopus 로고
    • Layout Impact of Resolution Enhancement Techniques: Impediment or Opportunity
    • L.W. Liebmann, "Layout Impact of Resolution Enhancement Techniques: Impediment or Opportunity", Proc. ACM/IEEE Intl. Symp. on Physical Design, 2003, pp. 110-117.
    • (2003) Proc. ACM/IEEE Intl. Symp. on Physical Design , pp. 110-117
    • Liebmann, L.W.1
  • 5
    • 33745787688 scopus 로고    scopus 로고
    • C. Webb, Layout Rule Trends and Affect upon CPU Design, Design and Process Integration for Microelectronic Manufacturing IV, edited by Alfred K. K. Wong, Vivek K. Singh, Proc. of SPIE 6156, 615602, (2006).
    • C. Webb, "Layout Rule Trends and Affect upon CPU Design", Design and Process Integration for Microelectronic Manufacturing IV, edited by Alfred K. K. Wong, Vivek K. Singh, Proc. of SPIE Vol. 6156, 615602, (2006).
  • 6
    • 84868991330 scopus 로고    scopus 로고
    • Documentation Version 2.4, Cadence Design Systems, Inc, June
    • Éclair-V2 Pattern Matcher User's Guide, Documentation Version 2.4, Cadence Design Systems, Inc., June 2008.
    • (2008) Éclair-V2 Pattern Matcher User's Guide
  • 9
    • 35148835527 scopus 로고    scopus 로고
    • Towards Manufacturability Closure: Process Variations and Layout Design
    • J. A. Torres, N.C. Berglund, Towards Manufacturability Closure: Process Variations and Layout Design, IEEE EDPS Workshop 2005.
    • (2005) IEEE EDPS Workshop
    • Torres, J.A.1    Berglund, N.C.2
  • 10
    • 33744954349 scopus 로고    scopus 로고
    • Litho-friendly design: A necessary complement to RET
    • May
    • Torres, J.A., "Litho-friendly design: a necessary complement to RET", Microlithography World, vol. 15, no. 2, pp. 10, 12-13A, May 2006.
    • (2006) Microlithography World , vol.15 , Issue.2
    • Torres, J.A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.