ESD concept for high-frequency circuits

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2008, Pages 221-227

  Issakov, Vadim ^a,b   Johnsson, David ^a   Cao, Yiqun ^a   Tiebout, Marc ^c   Mayerhofer, Michael ^a   Simbürger, Werner ^a   Maure, Linus ^d  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b UNIVERSITY OF PADERBORN   (Germany)

^c INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^d DICE GmbH & Co KG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PERFORMANCE; ESD PROTECTION DEVICES; HIGH FREQUENCY HF; ONCHIP INDUCTORS;

AUDIO FREQUENCY AMPLIFIERS; ELECTROSTATIC DISCHARGE; LOW NOISE AMPLIFIERS;

ELECTROSTATIC DEVICES;

EID: 66649108024     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. D. Linten et al., "A 5 GHz fully integrated ESDprotected Low-Noise Amplifier in 90 nm RF CMOS," in IEEE JSSCC, pp. 1434- 1442, July 2008.
2. W. Soldner et al., "A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection", in IEEE ISSCC Dig. Tech. Papers, pp. 550-551, 2007.
3. W. Soldner et al., "RF ESD Protection Strategies: Codesign vs. low-C protection", in Proc. EOS/ESD, 2005.
4. Y. Cao, V. Issakov, M. Tiebout "A 2 kV ESD protected 18 GHz LNA with 4 dB NF in 0.13 μm CMOS," in IEEE Proc. ISSCC, 2008.
5. J. Rautio, "Planar electromagnetic analysis," in Microwave Magazine (IEEE, ed.), vol. 4 of 1, pp. 35-41, 2003.
6. T. Schiml et al., "A 0.13 μm CMOS platform with Cu/low-k interconnect for system on chip applications," in IEEE Symp. VLSI Technology Dig. Tech. Papers, pp. 101-102, 2001. (Pubitemid 32950680)
7. M. Mergens et al., "Speed Optimized Diode-Triggered SCR (DTSCR) for RF ESD Protection of Ultra-Sensitive IC Nodes in Advanced Technologies," in IEEE Tran. on Device and Materials Reliability, vol. 5, no.3, pp. 532-542,Sep. 2005.
8. T. Maloney, N. Khurana "Transmission Line Pulsing for Circuit Modeling of ESD Phenomena," in Proc. on EOS/ESD Symp., pp. 49-54, 1985. (Pubitemid 17541002)
9. H. Gossner, "ESD protection for the deep sub micron regime - a challenge for design methodology," in Proc. on VLSI Design, pp. 809-818, 2004.
10. A. Ille, "Reliability aspects of gate oxide under ESD pulse stress," in Proc. EOS/ESD, 2007.