Robust wafer-level thin-film encapsulation of microstructures using low stress pecvd silicon carbide

Proceedings of the IEEE International Conference on Micro Electro Mechanical Systems (MEMS)

Volumn , Issue , 2009, Pages 140-143

  Rajaraman, V ^a   Pakula, L S ^a   Pham, H T M ^a   Sarro, P M ^a   French, P J ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BATCH PROCESSING; CHIP THICKNESS; CMOS COMPATIBLE; DEVICE GEOMETRIES; HARSH ENVIRONMENT; LOW STRESS; PECVD SIC; POST-CMOS; PROCESS COMPLEXITY; RF SWITCH; SEALING MATERIAL; THIN FILM ENCAPSULATION; WAFER LEVEL; WAFER-LEVEL ENCAPSULATION;

MEMS; MICROELECTROMECHANICAL DEVICES; MICROSTRUCTURE; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILICON CARBIDE;

SILICON WAFERS;

EID: 65949109309     PISSN: 10846999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMSYS.2009.4805338     Document Type: Conference Paper

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