A novel approach for stability analysis in carbon nanotube interconnects

IEEE Electron Device Letters

Volumn 30, Issue 5, 2009, Pages 475-477

  Fathi, Davood ^a   Forouzandeh, Behjat ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

Carbon nanotube (CNT); Interconnect; Nyquist; Stability

Indexed keywords

CONVERGENCE OF NUMERICAL METHODS; NANOTUBES; STABILITY; STABILITY CRITERIA; YARN;

CARBON NANOTUBE INTERCONNECTS; INTERCONNECT; NYQUIST; NYQUIST STABILITY CRITERION; RELATIVE STABILITIES; STABILITY ANALYSIS; TRANSMISSION LINE MODELING;

CARBON NANOTUBES;

EID: 65949088118     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2017388     Document Type: Article

References (13)

1. N. Srivastava and K. Banerjee, "Performance analysis of carbon nanotube interconnects for VLSI applications," in IEEE ICCAD, Santa Barbara, CA, Nov. 2005, pp. 383-390.
2. K. Banerjee and N. Srivastava, "Are carbon nanotubes the future of VLSI interconnections?" in Proc. ACM DAC, San Francisco, CA, Jul. 2006, pp. 809-814.
3. A. Naeemi and J. D. Meindl, "Design and performance modeling for single-walled carbon nanotubes as local, semiglobal, and global interconnects in gigascale integrated systems," IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 26-37, Jan. 2007.
4. N. Srivastava, R. V. Joshi, and K. Banerjee, "Carbon nanotube interconnects: Implications for performance, power dissipation and thermal management," IEEE Int. Electron Devices Meeting (IEDM , pp. 257-260, Dec. 2005, Washington, DC.
5. H. Li et al., "Circuit modeling and performance analysis of multi-walled carbon nanotube interconnects," IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1328-1337, Jun. 2008, Washington, DC.
6. A. Raychowdhury and K. Roy, "Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with cu interconnects for scaled technologies," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 1, pp. 58-65, Jan. 2006.
7. D. Fathi and B. Forouzandeh, "Time domain analysis of carbon nanotube interconnects based on distributed RLC model," Nano, Feb. 2009, to be published.
8. A. K. Palit, W. Anheier, and J. Schloeffel, "Reduced order long interconnect modeling," in ITG-GI-GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Timmendorfer Strand, Germany, Mar. 2003, pp. 42-47. 15.
9. K. Banerjee and A. Mehrotra, "An interconnect scaling scheme with constant on-chip inductive effects," Analog Integr. Circuits Signal Process., vol. 35, no. 2/3, pp. 97-105, May/Jun. 2003.
10. K. Banerjee and A. Mehrotra, "Analysis of on-chip inductance effects for distributed RLC interconnects," IEEE Trans. Comput.-Aided Design Integ. Circuits Syst., vol. 21, no. 8, pp. 904-915, Aug. 2002.
11. A. K. Palit, W. Anheier, and J. Schloeffel, "Estimation of signal integrity loss through reduced order interconnect model," in Proc. 7th IEEE Workshop Signal Propag. Interconnects IEEE-SPI, Siena, Italy, May 2003, pp. 163-166.
12. H. Aghababa and N. Masoumi, "Time-domain analysis of carbon nanotubes," in Proc. 7th Int. Caribbean Conf. Devices, Circuits Syst., Avignon, France, Apr. 2008, pp. 1-4.
13. A. Nieuwoudt and Y. Massoud, "Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2460-2466, Oct. 2006.