An interconnect scaling scheme with constant on-chip inductive effects

Analog Integrated Circuits and Signal Processing

Volumn 35, Issue 2-3, 2003, Pages 97-105

  Banerjee, Kaustav ^a   Mehrotra, Amit ^b  

^a University of California   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; ELECTRIC FIELDS; ELECTRIC RESISTANCE; INDUCTANCE; MAGNETIC FIELDS; VLSI CIRCUITS;

CONSTANT ON-CHIP INDUCTIVE EFFECTS; INTERCONNECT SCALING SCHEME;

INTERCONNECTION NETWORKS;

EID: 0042349706     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1024118330055     Document Type: Article

References (12)

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