Full-chip process window aware OPC capability assessment

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6730, Issue , 2007, Pages

  Lugg, Robert ^a   StJohn, Matt ^a   Zhang, Yunqiang ^a   Yang, Amy ^a   Van Adrichem, Paul ^a  

^a SYNOPSYS INC   (United States)

Author keywords

Layout DoE; OPC process window; Process window aware OPC

Indexed keywords

ADAPTIVE SYSTEMS; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; SYSTEMS ANALYSIS;

LAYOUT DOE; OPC PROCESS WINDOW; PROCESS WINDOW AWARE OPC;

MICROPROCESSOR CHIPS;

EID: 42149102807     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.746839     Document Type: Conference Paper

References (2)

1. Process design and Optical Proximity requirements for the 65nm device generation, K. Lucas et. al. Proc. of SPIE Vol. 5040, 2003.
2. Intelligent visualization of Lithography Violations, David Ziger et. al. Proc. of SPIE Vol. 6521, 2007