A new physics-based model for TANOS memories program/erase

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Mauri, A ^a   Compagnoni, C Monzio ^a,b   SAmoroso, ^a,b   Maconi, A ^a,b   Cattaneo, F ^a   Benvenuti, A ^a   Spinelli, A S ^b,c   Lacaita, A L ^b,c  

^a Numonyx   (Italy)

^b POLITECNICO DI MILANO   (Italy)

^c IFN CNR   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING/DETRAPPING; DEVELOPED MODELS; EXPERIMENTAL DATUM; EXTENDED RANGES; GATE STACKS; MODELING RESULTS; NEW PHYSICS; NITRIDE LAYERS; PROGRAM/ERASE; SIMULATED RESULTS;

NITRIDES;

ELECTRON DEVICES;

EID: 64549160558     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796749     Document Type: Conference Paper

References (7)

1. 3 with TaN metal gate for multi-giga bit flash memories," in IEDM Tech. Dig., pp. 613-616, 2003.
2. 2 cell size using TANOS (Si-Oxide- AbOs-TaN) cell technology," in IEDM Tech. Dig., pp. 29-32, 2006.
3. J. S. Sim, et al., "Self aligned trap-shallow trench isolation scheme for the reliability of TANOS TaN/AlO/SiN/Oxide/Si NAND Flash memory," in Proc. Non-Volatile Semiconductor Memory Workshop, pp. 110-111, 2007.
4. A. Furnemont, et al., "Physical understanding of SANOS disturbs and VARIOT engineered barrier as a solution," in Proc. Non-Volatile Semiconductor Memory Workshop, pp. 94-95, 2007.
5. 3-TaN )structure compatible to conventional NAND Flash memory," in Proc. Non-Volatile Semiconductor Memory Workshop, pp. 54-55, 2006.
6. 3 optimization for charge trap memory application," in Proc. ULIS, pp. 191-194, 2008.
7. D. Ielmini, et al., "Modeling of SILC based on electron and hole tunneling - Part II: Steady-state," IEEE Trans. Electron Devices, vol. 47, pp. 1266-1272, June 2000.