Self aligned trap-shallow trench isolation scheme for the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND flash memory

2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, Proceedings, NVSMW

Volumn , Issue , 2007, Pages 110-111

  Jae, Sung Sim ^a   Park, Jintaek ^a   Kang, Changseok ^a   Jung, Wonseok ^a   Shin, Yoocheol ^a   Kim, Juhyung ^a   Sel, Jongsun ^a   Lee, Changhyun ^a   Jeon, Sanghun ^a   Jeong, Younseok ^a   Park, Youngwoo ^a   Choi, Jungdal ^a   Lee, Won Seong ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 48649085873     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NVSMW.2007.4290602     Document Type: Conference Paper

References (3)

1. Y. Park et al., IEDM Tech. Dig., pp. 29-31, 2006.
2. J. S. Sim et al., ECS Int. Semi. Tech. Conf., Abst. No. 41, 2002.
3. C. Kang et al., IRPS Proc., pp. 167-170, 2007.