Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Miyashita, T ^a   Owada, T ^b   Hatada, A ^b   Hayami, Y ^a   Ookoshi, K ^b   Mori, T ^b   Kurata, H ^a   Futatsugi, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

^b Fujitsu Microelectronics Limited   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPRESSIVE STRAINS; DRIVE CURRENTS; ELECTRICAL ANALYSIS; ELECTRICAL CHARACTERIZATIONS; HIGH-PERFORMANCE APPLICATIONS; KEY FACTORS; METAL GATES; OFFSET SPACERS; PARASITIC RESISTANCES; PHYSICAL ANALYSIS; POLY GATES; SMT PROCESS; STRESS MEMORIZATION TECHNIQUES; VERTICAL DIRECTIONS; VOLUME EXPANSIONS;

ARSENIC; DIFFUSERS (OPTICAL); ELECTRON DEVICES; GRAIN GROWTH; PHOSPHORUS; SURFACE MOUNT TECHNOLOGY;

ELECTRIC NETWORK ANALYSIS;

EID: 64549146610     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796612     Document Type: Conference Paper

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