Advanced methodologies for backside circuit edit

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2008, Pages 305-314

  O'Donnell, E ^a   Scott, D ^a   Malik, T ^b   Jain, R ^b   Lundquist, T ^b   Schlangen, R ^c   Kerst, U ^c   Bolt, C ^c  

^a INTEL CORPORATION   (United States)

^b DCG SYSTEMS INC   (United States)

^c TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT EDITS; CIRCUIT NODES; FLIP CHIPS; FOCUSED-ION-BEAM SYSTEMS; NEW DEVICES; ON CHIPS; PROCESS TECHNOLOGIES; TRANSISTOR LEVELS;

FOCUSED ION BEAMS; INTEGRATED CIRCUITS; QUALITY ASSURANCE; SAFETY FACTOR;

FAILURE ANALYSIS;

EID: 63549145842     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1361/cp2008istfa305     Document Type: Conference Paper

References (11)

1. th ISTFA (2002) 409
2. th ESREF (2005) 1544
3. th ITC (2004) 48.2
4. th ESREF (2005) 1544
5. R.K. Jain, T. Malik, T. Lundquist, C-C. Tsao, W. Walecki "Advanced Fringe Analysis Techniques in Circuit Edit " Proc. ISTFA (2006) 79
6. th ESREF (2006) 1498
7. S. Tyagi et al, "An Advanced Low Power, High Performance, Strained Channel 65nm Technology " Proc. IEEE International Electron Devices Meetings (2005)
8. CK Cheng, private communication 2003.
9. T. Malik, R. Jain, R. Nicholson, T. Lundquist "Role of Circuit Edit in Post-Silicon Debug and Diagnosis " Proc. IEEE Silicon Debug & Diagnosis (2005)
10. No reference, needs to be added.
11. No reference, needs to be added