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Volumn , Issue , 2005, Pages 1964-1967

Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN AND OPTIMIZATION; HIGH RESOLUTION; LOW POWER; MULTI-BIT; OPTIMAL DESIGN; PIPELINE ADC; PIPELINE ADCS; PIPELINED ADCS; TOTAL POWER CONSUMPTION;

EID: 63449096083     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464999     Document Type: Conference Paper
Times cited : (10)

References (7)
  • 1
    • 0026901915 scopus 로고
    • Optimizing the stage resolution in pipelined, multi-stage, analog-to-digital converters for video-rate applications
    • Aug
    • S. Lewis, "Optimizing the stage resolution in pipelined, multi-stage, analog-to-digital converters for video-rate applications," IEEE Trans. Circuits Syst. II, vol. 39, Aug. 1992.
    • (1992) IEEE Trans. Circuits Syst. II , vol.39
    • Lewis, S.1
  • 2
    • 67649093026 scopus 로고    scopus 로고
    • P. Quinn, M. Pribytko, A. van Roermund, Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion, in Analog Circuit Design, Kluwer Academic Publishers, ISBN 1-4020-2786-9 (HB), 2004, pp.327-349.
    • P. Quinn, M. Pribytko, A. van Roermund, "Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion," in "Analog Circuit Design," Kluwer Academic Publishers, ISBN 1-4020-2786-9 (HB), 2004, pp.327-349.
  • 3
    • 0242611936 scopus 로고    scopus 로고
    • Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 mm CMOS
    • San Jose, Sept
    • P. Quinn, M. Pribytko, "Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 mm CMOS," in proc. IEEE 2003 Custom Integrated Circuits Conf., San Jose, Sept. 2003, pp.425-428.
    • (2003) proc. IEEE 2003 Custom Integrated Circuits Conf , pp. 425-428
    • Quinn, P.1    Pribytko, M.2
  • 5
    • 0032626968 scopus 로고    scopus 로고
    • Power optimization for pipeline analog-todigital converters,
    • May
    • P. Kwok and H. Luong, "Power optimization for pipeline analog-todigital converters,", IEEE Trans. Circuits Syst. II, vol 46, May 1999.
    • (1999) IEEE Trans. Circuits Syst. II , vol.46
    • Kwok, P.1    Luong, H.2
  • 6
    • 0032259908 scopus 로고    scopus 로고
    • Systematic design for optimization of high-speed self-calibrated pipelined A/D converters
    • Dec
    • J. Goes, J. Vital, and J. Franca, "Systematic design for optimization of high-speed self-calibrated pipelined A/D converters," IEEE Trans. Circuits Syst. II, vol. 45, Dec. 1998.
    • (1998) IEEE Trans. Circuits Syst. II , vol.45
    • Goes, J.1    Vital, J.2    Franca, J.3
  • 7
    • 49749108690 scopus 로고    scopus 로고
    • Accuracy limitations of pipelined ADCs
    • May, Kobe, Japan
    • P. Quinn and A. van Roermund, "Accuracy limitations of pipelined ADCs," in proc. IEEE 2005 ISCAS, May 2005, Kobe, Japan.
    • (2005) proc. IEEE 2005 ISCAS
    • Quinn, P.1    van Roermund, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.