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Volumn , Issue , 2005, Pages 1964-1967
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Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs
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Author keywords
[No Author keywords available]
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Indexed keywords
DESIGN AND OPTIMIZATION;
HIGH RESOLUTION;
LOW POWER;
MULTI-BIT;
OPTIMAL DESIGN;
PIPELINE ADC;
PIPELINE ADCS;
PIPELINED ADCS;
TOTAL POWER CONSUMPTION;
ANALOG TO DIGITAL CONVERSION;
ERROR ANALYSIS;
PIPELINES;
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EID: 63449096083
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2005.1464999 Document Type: Conference Paper |
Times cited : (10)
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References (7)
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