Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25μm CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 425-427

  Quinn, Patrick ^a   Pribytko, Maxim ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; BUFFER CIRCUITS; CALIBRATION; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; ELECTRIC POTENTIAL; TRANSFER FUNCTIONS;

CHARGE TRANSFER CIRCUIT; SWITCHED CAPACITOR;

ANALOG TO DIGITAL CONVERSION;

EID: 0242611936     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. Li, M. Chin, P. Gray, R. Castello, "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique", IEEE J. Solid-State Circuits, vol. SC-19, No. 6, pp. Dec. 1984.
2. B-S Song, M. Tompsett, K. Lakshmikumar, "A 12-bit 1-Msample/s Capacitor Error-Averaging Pipelined A/D Converter." IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1324-1332, Dec. 1988.
3. A. Abo, P. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter", IEEE J. Solid-State Circuits, vol. 34, No. 5, pp. 599-606, May 1999.
4. D. Cline and P. Gray, "A Power Optimized 13-b 5 Msamples/s Pipelined Analog-to-Digital Converter in 1.2 μm CMOS," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 294-303, Mar, 1996.
5. O. Erdogan, P. Hurst, S. Lewis, "A 12-b Digital-Background-Calibrated Algorithmic ADC with -90-dB THD", IEEE J. Solid State Circuits, vol. 34, no. 12, pp. 1812-1820, Dec, 2001.