Accuracy limitations of pipelined ADCs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1956-1959

  Quinn, Patrick J ^a   Van Roermund, Arthur H M ^b  

^a XILINX INC   (United States)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURACY LIMITATIONS; ERROR BOUND; KEY CHARACTERISTICS; OPTIMIZED DESIGNS; PIPELINE ADC; PIPELINED ADC; PIPELINED ADCS; SWITCHED CAPACITOR; TRANSFER CHARACTERISTICS;

MULTICARRIER MODULATION;

EID: 49749108690     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464997     Document Type: Conference Paper

References (4)

1. S. Lewis, "Optimizing the stage resolution in pipelined, multi-stage, analog-to-digital converters for video-rate applications," IEEE Trans. Circuits Syst. II, vol. 39, Aug. 1992.
2. P. Quinn, M. Pribytko, A. van Roermund, "Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion," in "Analog Circuit Design," Kluwer Academic Publishers, ISBN 1-4020-2786-9 (HB), 2004, pp.327-349.
3. Thomas B. Cho and Paul R. Gray, "A 10 b, 20 Msample/s, 35mW Pipeline A/D Converter," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar, 1995.
4. J. Goes, J. Vital, and J. Franca, "Systematic design for optimization of high-speed self-calibrated pipelined A/D converters," IEEE Trans. Circuits Syst. II, vol. 45, Dec. 1998.