The use of stressed silicon in MOS transistors and CMOS structures

Russian Microelectronics

Volumn 38, Issue 2, 2009, Pages 71-86

  Neizvestnyi, I G ^a   Gridchin, V A ^b  

^a INSTITUTE OF SEMICONDUCTOR PHYSICS   (Russian Federation)

^b NOVOSIBIRSK STATE TECHNICAL UNIVERSITY   (Russian Federation)

Author keywords

[No Author keywords available]

Indexed keywords

GERMANIUM; MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SILICON ALLOYS; SILICON NITRIDE; STRESSES; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

CMOS STRUCTURES; ELECTRONIC PROCESS; MECHANICAL STRESS; MOS TRANSISTORS; SOURCE AND SINKS; STRESSED SILICONS; TRANSISTOR OPERATIONS;

SEMICONDUCTING SILICON;

EID: 63449084868     PISSN: 10637397     EISSN: None     Source Type: Journal    
DOI: 10.1134/S1063739709020012     Document Type: Article

References (36)

1. Krasnikov, G.Ya., Konstructivno-tekhnologicheskie osobennosti submikronnykh MOP-transistors (Constructive and Technological Features of Submicron MOS Transistors), Moscow: Tekhnosfera, Part 1 2002, Part 2 2004.
2. Orlikovskii, A.A., Silicon Transistor Nanoelectronics, Izv. Vyssh. Uchebn. Zaved., Elektronika, 2006, no. 5, pp. 35-44.
3. Skotnicki, T. and Monfray, S., Materials and MOS Device Architectures for Sub-32 nm CMOS Nodes, Proc. Int. Conf. on Micro- and Nanoelectronics - 2007 (ICMNE-2007), Moscow-Zvenigorod, 2007, p. L1-01.
4. Gridchin, V.A. and Dragunov, V.P., Fizika mikrosistem (Physics of Microsystems), Part 1, Novosibirsk: NGTU, 2004.
5. Smith, C.S., Piezoresistance Effect in Germanium and Silicon, Phys. Rev., vol. 94, no. 1, p. 4249.
6. Aleinikov, A.F., Gridchin, V.A., and Tsapenko, M.P., Datchiki (Sensors), Novosibirsk: NGTU, 2003.
7. Taskin, A.A., Gridchin, V.A., Cherepov, E.I., et al., Pressure Sensors of the Membrane Type for the Investigation of Aerodynamic Flows, Nauka-Proizvodstvu, 2001, no. 12 (50), pp. 26-30.
8. Baranskii, P.I., Klochkov, V.P., and Potykevich, I.V., Poluprovodnikovaya elektronika. Spravochnik (Semiconductor Electronics. Handbook), Kiev: Naukova Dumka, 1975.
9. Arghani, R. et al., Abstracts of Papers, Int. Seminar on Strain Engineering in Non-Volatile Memories, April 2006, p. 32.
10. J.C. Hensel G. Feher 1963 Cyclotron Resonance Experiments in Uniaxially Stressed Silicon: Valence Band Inverse Mass Parameters and Deformation Potential Phys. Rev. 129 3 1041 1062
11. x Alloy Films on (100) Si Appl. Phys. Lett. 41 5 464 466
12. 1-x /Si Strained Layer Heterostructures Appl. Phys. Lett. 45 11 1231 1233
13. Rim, K. et al., Abstracts of Papers, VLSI Symp., June 2002, pp. 98-99.
14. Wang, H.C. et al., Proc. IEDM Tech. Dig., Dec. 2002, pp. 61-64.
15. Lee, B.H. et al., Proc. IEDM Tech. Dig., Dec. 2003, pp. 946-948.
16. Rim, K. et al., Fabrication and Mobility Characteristics of Ultra Thin Strained-Si Directly on Insulator (SSDOI) MOSFETs, Proc. IEDM Tech. Dig., Dec. 2003, pp. 49-52.
17. Semenova, O. et al., Poverkhnost, 1992, issue 9-11.
18. Ito, S. et al., Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design, Proc. IEDM Tech. Dig., Dec. 2000.
19. Yang, Y.S. et al., Proc. IEDM Tech. Dig., Dec. 2004, pp. 1075-1078.
20. Shimitzu, A. et al., Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement, Proc. IEDM Tech. Dig., Dec. 2003.
21. Ota, K. et al., Novel Locally Strained Technique for Performance 55 nm CMOS, Proc. IEDM Tech. Dig., Dec. 2002, pp. 27-30.
22. Chen, C.H. et al., Abstracts of Papers, VLSI Symp., June 2004, pp. 56-57.
23. Khamankar, R. et al., Abstracts of Papers, VLSI Symp., June 2004, pp. 162-163.
24. Ghani, T. et al., A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistor, Proc. IEDM Tech. Dig., Dec. 2003, pp. 978-980.
25. Mistry, K. et al., Abstracts of Papers, VLSI Symp., June 2004, pp. 50-51.
26. Bai et al., Proc. IEDM Tech. Dig., Dec. 2004, pp. 657-660.
27. Sato 1971 Phys. Rev. B: Condens. Matter 4 1950 1960
28. Chan, V. et al., Strain for CMOS Performance Improvement, Proc. IEEE 2005 Custom Integrated Circuits Conf., 2005.
29. Yang, M. et al., High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations, Proc. IEDM Tech. Dig., Dec. 2003, pp. 453-456.
30. Yang, M. et al., Abstracts of Papers, VLSI Symp., June 2004, pp. 160-161.
31. L. Chang 2004 CMOS Circuit Performance Enhancement by Surface Orientation Optimization Trans. Elec. Dev. 51 1621 1627
32. Washington, L. et al., p-MOSFET with 200% Mobility Enhancement Induced by Multiple Stressors, IEEE Electron Dev. Lett., 2006, vol. 27, no. 6.
33. Horstmann, M. et al., Integration and Optimization of Embedded-SiGe, Compressive and Tensile Stressed Liner Films, and Stress Memorization in Advanced SOI CMOS Technologies, IEDM Tech. Dig., Dec. 2005, Report 5, Session 10.
34. Singer, P., No More Technology Nodes in New ITRS, Semic. Intern., Jan. 2006, pp. 13-14.
35. Peters, L., Roadmapping 2006 to the Post-CMOS Era, Semic. Intern., March 2006, pp. 17-18.
36. James, D., Strained Silicon to High-k and Metal Gate, Sol. St. Tech., Nov. 2007.