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Volumn 12, Issue 10, 2004, Pages 1066-1075

Empirical models for net-length probability distribution and applications

Author keywords

Empirical modeling; Interconnect prediction; Multiterminal nets; Probabilistic modeling

Indexed keywords

BENCHMARKING; CROSSTALK; OPTIMIZATION; PROBABILITY; WIRE;

EID: 6344287275     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.834235     Document Type: Conference Paper
Times cited : (6)

References (16)
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    • A. Agarwal et al., "Computation and refinement of statistical bounds on circuit delay," in Proc. Design Automation Conf., June 2003, pp. 348-353.
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    • Agarwal, A.1
  • 6
    • 0035789680 scopus 로고    scopus 로고
    • A priori system-level interconnect prediction: Rent's rule and wire length distribution models
    • D. Stroobandt, "A priori system-level interconnect prediction: Rent's rule and wire length distribution models," in Proc. Int. Workshop System-Level Interconnect Prediction, 2001, pp. 3-21.
    • (2001) Proc. Int. Workshop System-level Interconnect Prediction , pp. 3-21
    • Stroobandt, D.1
  • 7
    • 0035789304 scopus 로고    scopus 로고
    • Multi-terminal nets do change conventional wire length distribution models
    • _, "Multi-terminal nets do change conventional wire length distribution models," in Proc. Int. Workshop System-Level Interconnect Prediction, 2001, pp. 41-48.
    • (2001) Proc. Int. Workshop System-level Interconnect Prediction , pp. 41-48
  • 8
    • 0032025521 scopus 로고    scopus 로고
    • A stochastic wire-length distribution for gigascale integration (GSI): Part II: Applications to clock frequency, power dissipation, and chip size estimation
    • Mar.
    • J. A. Davis, V. K. De, and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI): Part II: Applications to clock frequency, power dissipation, and chip size estimation," IEEE Trans. Electron Devices, vol. 45, pp. 590-597, Mar. 1998.
    • (1998) IEEE Trans. Electron Devices , vol.45 , pp. 590-597
    • Davis, J.A.1    De, V.K.2    Meindl, J.D.3
  • 11
    • 0025594311 scopus 로고
    • Buffer placement in distributed RC-tree networks for minimal Elmore delay
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    • L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. Int. Symp. Circuits Systems, Dec. 1990, pp. 865-868.
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    • Van Ginneken, L.P.P.P.1
  • 13
    • 0035181641 scopus 로고    scopus 로고
    • Fixed-outline floorplanning through better local search
    • S. Adya and I. Markov, "Fixed-outline floorplanning through better local search," in Proc. IEEE Int. Conf. Computer Design, 2001, pp. 321-334.
    • (2001) Proc. IEEE Int. Conf. Computer Design , pp. 321-334
    • Adya, S.1    Markov, I.2
  • 14
    • 0041633858 scopus 로고    scopus 로고
    • Parameter variations and impact on circuits and microarchitecture
    • June
    • S. Borkar et al., "Parameter variations and impact on circuits and microarchitecture," in Proc. Design Automation Conf., June 2003, pp. 338-342.
    • (2003) Proc. Design Automation Conf. , pp. 338-342
    • Borkar, S.1
  • 16
    • 34748823693 scopus 로고
    • The transient analysis of damped linear networks with particular regard to wideband amplifiers
    • W. C. Elmore, "The transient analysis of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, no. 1, pp. 55-63, 1948.
    • (1948) J. Appl. Phys. , vol.19 , Issue.1 , pp. 55-63
    • Elmore, W.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.