Opto-WLP for CMOS imaging sensors

Semiconductor International

Volumn 29, Issue 13, 2006, Pages

  Garrou, Philip ^a,b  

^a IEEE   (United States)

^b RTI INTERNATIONAL   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COEFFICIENT OF THERMAL EXPANSION (CTE); RESIST MASK; WAFER-LEVEL PACKAGING (WLP);

CMOS INTEGRATED CIRCUITS; IMAGE SENSORS; OPTICAL PROPERTIES; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILICON WAFERS; THERMAL EXPANSION;

ELECTRONICS PACKAGING;

EID: 33846220333     PISSN: 01633767     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (7)

1. C. Scanlan and N. Karim, "System-in-Package Technology Applications and Trends." Proc. SMTA Conf. Polymers and Adhesives, 2001.
2. J. Leib and M. Toepper, "New Wafer Level Packaging Technology Using Silicon-Via-Contacts for Optical and Other Sensor Applications," 54th Elec. Comp. Tech. Conf., 2004, p. 843.
3. J. Leib, D. Mund and M. Toepper, "Novel Hermetic Wafer Level Packaging Technology Using Low Temperature Passivation," 55th Elec. Comp. Tech. Conf., 2005, p. 562.
4. P. Garrou, "Wafer-Level Packaging Has Arrived," Semiconductor International, October 2000, Vol. 23, No. 10, p. 119.
5. M. Toepper and P. Garrou, "The Wafer-Level Packaging Evolution," Semiconductor International, October 2004, Vol. 27, No. 10, p. SP-13.
6. P Garrou, "Wafer Level Chip Scale Packaging: An Overview," IEEE Trans. Advanced Packaging, 2000, Vol. 23, p. 198.
7. D. Mund and J. Leib, "Novel Microstructuring Technology for Glass on Silicon and Glass Substrates," 54th Elec. Comp Tech. Conf., 2004, p. 939.