MPI as an Abstraction for Software-Hardware Interaction for HPRCs

Proceedings - 2nd International Workshop on High-Performance Reconfigurable Computing Technology and Applications, HPRCTA 2008 - Held in Conjunction with SC08

Volumn , Issue , 2008, Pages

  Saldaña, Manuel ^a   Patel, Arun ^a   Madill, Christopher ^c   Nunes, Daniel ^b   Wang, Danyao ^b   Styles, Henry ^d   Putnam, Andrew ^d   Wittig, Ralph ^d   Chow, Paul ^b  

^a Arches Computing Systems   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c UNIVERSITY OF TORONTO   (Canada)

^d XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANCE; INFORMATION THEORY; MICROPROCESSOR CHIPS; PARALLEL ARCHITECTURES; QUALITY ASSURANCE;

DESIGN CHALLENGES; EASE OF USE; HARDWARE/SOFTWARE CO DESIGNS; LEARNING CURVES; LEGACY CODES; MULTIPROCESSOR SYSTEMS ON CHIPS; NEW DESIGNS; PROGRAMMING MODELS; RE-CONFIGURABLE; RECONFIGURABLE COMPUTERS; SYSTEM LEVELS; TIGHTLY-COUPLED;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 62949206616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPRCTA.2008.4745682     Document Type: Conference Paper

References (38)

1. The MPI Forum, "MPI: a message passing interface," in Supercomputing '93: Proceedings of the 1993 ACM/IEEE conference on Supercomputing. New York, NY, USA: ACM Press, 1993, pp. 878-883.
2. Intel, "Intel Quick Path Architecture (White Paper)," http://www.intel. com/technology/quickpath/whitepaper.pdf [Accessed: September, 2008].
3. HyperTransport Consortium, http://www.hypertransport.org.
4. Cray Inc., CRAY XD1 FPGA Development, 2005, pp. 9-11, pp. 63-66.
5. SGI, Reconfigurable Application-Specific Computing Users Guide, Jan 2008, pp. 9-12, pp. 223-244.
6. "OpenFPGA," http://www.openfpga.org/.
7. Manuel Saldaña, "A Parallel Programming Model for a Multi-FPGA Multiprocessor Machine," Master's thesis, University of Toronto, 2006.
8. M. Saldaña and P. Chow, "TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs," in Proceedings of the 16th International Conference on Field-Programmable Logic and Applications, Madrid, Spain, 2006.
9. M. Saldaña, D. Nunes, E. Ramalho, and P. Chow, "Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI," in In the Proc. of the 3rd Intl. Conf. on Reconfigurable Computing and FPGAs., San Luis Potosi, Mexico, 2006.
10. A. Patel, C. A. Madill, M. Saldana, C. Comis, R. Pomes, and P. Chow, "A Scalable FPGA-based Multiprocessor," Field-Programmable Custom Computing Machines, 2006. FCCM'06. 14th Annual IEEE Symposium on, pp. 111-120, April 2006.
11. Cray, Inc., "Cray XD1 Supercomputer for Reconfigurable Computing," http://www.cray.com/downloads/FPGADatasheet.pdf [Accessed: Sept. 2008].
12. Nallatech, Inc., http://www.nallatech.com/.
13. SRC Computers, Inc., http://www.srccomp.com/.
14. DRC computer, http://www.drccomputer.com/.
15. Xtreme Data Inc., http://www.xtremedatainc.com/.
16. D. Callahan, B. Chamberlain, and H. Zima, "The Cascade High Productivity Language," Proc. Ninth Intl. Workshop on High-Level Parallel Programming Models and Supportive Environments., pp. 52-60, April 2004.
17. Ebcioglu, Saraswat, and Sarkar, "X10: an Experimental Language for High Productivity Programming of Scalable Systems," Productivity and Performance in High-End Computing (P-PHEC). Second International Workshop on, February 2005.
18. Impulse Accelerated Technologies, Inc., http://www.impulsec.com.
19. Celoxica, LTD., http://www.celoxica.com.
20. Synfora, Inc., http://www.synfora.com.
21. Mitrionics, Inc., http://www.mitrionics.com.
22. W. Gropp, E. Lusk, N. Doss, and A. Skjellum, "A High-Performance, Portable Implementation of the MPI Message Passing Interface Standard," Parallel Computing, vol. 22, no. 6, pp. 789-828, Sept. 1996.
23. R. L. Graham, T. S. Woodall, and J. M. Squyres, "Open MPI: A Flexible High Performance MPI," in Proceedings, 6th Annual Intl. Conf. Parallel Processing and Applied Mathematics, Poznan, Poland, Sept. 2005.
24. Amirix Systems, Inc., http://www.amirix.com/.
25. C. Chang, J. Wawrzynek, and R. W. Brodersen, "BEE2: A High-End Reconfigurable Computing System," IEEE Des. Test'05, vol. 22, no. 2, pp. 114-125, 2005.
26. A. Jerraya and W. Wolf, Eds., Multiprocessor Systems-on-Chip. Morgan Kaufmannn, 2004.
27. V. Aggarwal, I. A. Troxel, and A. D. George, "Design and Analysis of Parallel N-Queens on Reconfigurable Hardware with Handel-C and MPI," in 2004 MAPLD Intl. Conference, Washington, DC, USA, 2004.
28. "OpenFPGA GenAPI version 0.4 Draft For Comment," http://www. openfpga.org/pages/Standards.aspx [Accessed: September, 2008].
29. Intel, "Intel QuickAssist Technology AAL (White Paper)," http://download.intel.com/technology/platforms/quickassist/quickassist aal whitepaper.pdf [Accessed: September, 2008].
30. M. Jones, L. Scharf, J. Scott, C. Twaddle, M. Yaconis, K. Yao, P. Athanas, and B. Schott, "Implementing an API for Distributed Adaptive Computing Systems," in FCCM'99: Proc. of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Washington, DC, USA, 1999, p. 222.
31. N. Moore, A. Conti, M. Leeser, and L. King, "Vforce: An Extensible Framework for Reconfigurable Supercomputing," Computer, vol. 40, no. 3, pp. 39-49, March 2007.
32. C. Comis, "A High-Speed Inter-Process Communication Architecture for FPGA-based Hardware Acceleration of Molecular Dynamics," Master's thesis, University of Toronto, 2005.
33. MPI Parallel Environment, http://www-unix.mcs.anl.gov/perfvis/ software/MPE/index.htm [Accessed: Sept. 2008].
34. O. Zaki, E. Lusk, W. Gropp, and D. Swider, "Toward scalable performance visualization with Jumpshot," High Performance Computing Applications, vol. 13, no. 2, pp. 277-288, Fall 1999.
35. D. Nunes, M. Saldaña, and P. Chow, "A Profiler for a Heterogeneous Multi-Core Multi-FPGA System," in In Proceedings of the 2008 Intl. Conference on Field-Programmable Technology, Taipei, Taiwan, 2008.
36. M. Saldaña, E. Ramalho, and P. Chow, "A Message-passing Hardware/ Software Co-simulation Environment to Aid in Reconfigurable Computing Design using TMD-MPI," in In Proc. of the 5th Intl. Conf. on Reconfigurable Computing and FPGAs., Cancun, Mexico, 2008.
37. Mentor Graphics, Corp., http://www.mentor.com/.
38. D. Wang, "An Automated Flow to Generate Hardware Computing Nodes from C for an FPGA-Based MPI Computing Network," Engineering Science Undergraduate Thesis, University of Toronto, 2008.