TMD-MPI: An MPI implementation for multiple processors across multiple FPGAS

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 329-334

  Saldaña, Manuel ^a   Chow, Paul ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (STANDARDS); CODES (SYMBOLS); DATA STORAGE EQUIPMENT; ELECTRIC NETWORK TOPOLOGY; FUZZY LOGIC; INTEGRATED CIRCUITS; INTERNET PROTOCOLS; MESSAGE PASSING; STANDARDS;

CODE PORTABILITY; EMBEDDED PROCESSORS; FIELD PROGRAMMABLE LOGIC (FPL); HARDWARE COMPLEXITIES; INTELLECTUAL PROPERTY BLOCK (IP BLOCK); INTERNATIONAL CONFERENCES; LINK BANDWIDTHS; LOW OVERHEAD; MASSIVE PARALLELISM; MEMORY UNITS; MESSAGE PASSING INTERFACE (MPI); MICROBENCHMARKS; MPI IMPLEMENTATION; MULTIPLE PROCESSORS; MULTIPROCESSOR EMBEDDED SYSTEM; NETWORK-ON-CHIP (NOC); OPERATING SYSTEMS; PARALLEL CODING; PERFORMANCE PARAMETERS; PROGRAMMING MODELS; SINGLE CHIPS; SMALL MEMORY FOOTPRINTS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 46249129709     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311233     Document Type: Conference Paper

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