A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 17-20

  Kim, Young Ju ^a   Choi, Hee Cheol ^a   Yoo, Pil Seon ^a   Lee, Dong Suk ^a   Choi, Joong Ho ^b   Lee, Seung Hoon ^a  

^a Sogang University   (South Korea)

^b University of Seoul   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGIES; DIE AREAS; EFFECTIVE NUMBER OF BITS; LOW OFFSETS; LOW-POWER CONSUMPTION; OFFSET VOLTAGES; POWER-SUPPLY VOLTAGES; RAIL TO RAILS; RAIL-TO-RAIL INPUTS; SINGLE-ENDED; VOLTAGE REFERENCES;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; MULTICARRIER MODULATION;

RAILS;

EID: 62949175298     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4745949     Document Type: Conference Paper

References (8)

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