A single die 124dB stereo audio delta sigma ADC with 111dB THD

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 252-255

  Yang, YuQing ^a,b   Sculley, Terry ^a   Abraham, Jacob ^b  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; CMOS INTEGRATED CIRCUITS; DATA HANDLING; DIES; ELECTRIC FILTERS; ELECTRIC POWER UTILIZATION; INDUSTRIAL MANAGEMENT; MEASUREMENTS; MODULATORS; MULTICARRIER MODULATION; NETWORKS (CIRCUITS);

BANDGAP REFERENCE (BGR); CHANNEL ISOLATION; DECIMATION FILTERING; DELTA-SIGMA; DELTA-SIGMA ADC; DYNAMIC RANGE (DR); EUROPEAN; FEEDFORWARD PATHS; HIGH PERFORMANCE; HIGH-PRECISION (LARGE SIGNAL TO NOISE RATIO) MEASUREMENT; INTERNAL CHANNELS; LOW-POWER CONSUMPTION; NEW TECHNIQUES; ON CHIPS; POWER CONSUMPTION (CE); QUANTIZATION LEVELS; QUANTIZER; SINGLE LOOP; SOLID-STATE CIRCUITS CONFERENCE; STEREO AUDIO; THREE LEVEL; TOTAL POWER CONSUMPTION;

ENERGY RESOURCES;

EID: 44849108987     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430291     Document Type: Conference Paper

References (6)

1. I. Fujimori, K. Koyama, D. Trager, F. Tam, and L. Longo, "A 5V single-chip Delta-Sigma audio A/D converter with 111 dB dynamic range," Proc. 1996 IEEE CICC, May 1996.
2. I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S. Chan, "A 90-dB SNR 2.5-MHz output rate ADC using cascaded multibit delta sigma, modulation 8x oversampling ratio," ISSCC2000.
3. Lukas, et al, "3mW, 74dB SNR 2MHz Continuous time Delta-Sigma ADC with a tracking ADC Quantizer in 0.13um CMOS", ISSCC 2005.
4. Steven R, et.al, "Delta-Sigma Data Converters, Theory Design and Simulation", IEEE press 1997, pp.262.
5. 2", ISSCC 2003.
6. AK5394 datasheet, Asahi Kasei Microelectronics, Inc.