A calibration-free 3V 16b 500kS/s 6mW 0.5mm2 ADC with 0.13μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 76-77

  Choi, Hee Cheol ^a   You, Seung Bin ^a   Lee, Ho Young ^a   Park, Ho Jin ^a   Kim, Jae Whui ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Calibration free; Cyclic ADC; High resolution

Indexed keywords

BANDWIDTH; CALIBRATION; CAPACITORS; ELECTRIC CURRENTS; ERROR CORRECTION; NETWORKS (CIRCUITS);

CALIBRATION-FREE; CYCLIC ADC; DIGITAL CORRECTION LOGIC (DCL); HIGH-RESOLUTION;

CMOS INTEGRATED CIRCUITS;

EID: 4544347725     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A. Kitagawa, et al., "A 10b, 3Msample/s CMOS Cyclic ADC," ISSCC Dig. Tech. Papers, pp. 280-281, Feb. 1995.
2. Jungwook Yang and Hae-Seung Lee, "A CMOS 12-bit 4MHz Pipelined A/D Converter with Commutative Feedback Capacitor," Proc. CICC, pp 427-430, May 1996.
3. S. H. Lee and B. S. Song, "Digital-Domain Calibration of Multi-Step Analog-to-Digital Converters," IEEE J. Solid-State Circuits, vol. 27, no. 6, pp 1679-1688, Dec. 1992.