High throughput 32-bit AES implementation in FPGA

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 1806-1809

  Chang, Chi Jeng ^a   Huang, Chi Wu ^b   Chang, Kuo Huang ^a   Chen, Yi G ^b   Hsieh, Chung Cheng ^a  

^a Institute of Applied Electronics Technology   (Taiwan)

^b NATIONAL TAIWAN NORMAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCE ENCRYPTION STANDARDS; EMBEDDED HARDWARES; HARDWARE IMPLEMENTATIONS; HIGH THROUGHPUTS; LOW AREAS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; WATER WELL PUMPS;

THROUGHPUT;

EID: 62949153692     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4746393     Document Type: Conference Paper

References (10)

1. NIST. Announcing the advanced encryptionstandard(AES), FIPS 197. Technical report, National Institute of Standards and Technology, November 2001.
2. Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, and Hung-Yun Tai, "The FPGA Implementation of 128-bits AES Algorithm Based on Four 32-bits Parallel Operation," IEEE Computer Society, pp.462-464. 2007.
3. T. Good and M. Benaissa "Pipelined AES on FPGA with support for feedback modes (in a multi-channel environment)," in the Institution of Engineering and Technology, Vol. 1, No. 1. pp. 1-10 March 2007.
4. Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, and Leonel Sousa, "Reconfigurable Memory Based AES Co-Processor," IPDPS 2006. 20th International Parallel and Distributed Processing Symposium 2006.
5. A. Hodjat, "Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors," IEEE Transactions On Computers, vol. 55, NO. 4, pp. 366-372. April 2006.
6. A. Hodjat and I. Verbauwhede, "Interfacing a high speed crypto accelerator to an embedded cpu," In Proc. 38th Asilomar Conference on Signals, Systems, and Computers, volume 1, pp. 488-492. November 2004.
7. Pawel Chodowiec and Kris Gaj, "Very Compact FPGA Implementation of the AES Algorithm", CHES 2003.
8. G. Rouvroy, F.-X. Standaert, J.-J. Quisquater and J.-D. Legat, "Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications", Information Technology Coding and Computing, 2004.
9. Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, Hung-Yun Tai, "Compact FPGA Implementation of 32-bits AES Algorithm Using Block RAM," The IEEE international technical conference sponsored from 30 October to 2 November 2007.
10. Xilinx web site http://www.xilinx.com/.