Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors

IEEE Transactions on Computers

Volumn 55, Issue 4, 2006, Pages 366-372

  Hodjat, Alireza ^a   Verbauwhede, Ingrid ^b  

^a BROADCOM CORPORATION   (United States)

^b FACULTÉ POLYTECHNIQUE DE MONS   (Belgium)

Author keywords

Advanced Encryption Standard (AES); ASIC; Crypto processor; Cryptography; Hardware architectures; Security; VLSI

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; CRYPTOGRAPHY; DESIGN; OPTIMIZATION; SECURITY OF DATA; VLSI CIRCUITS;

ADVANCED ENCRYPTION STANDARD (AES); CRYPTO-PROCESSOR; HARDWARE ARCHITECTURE;

PIPELINE PROCESSING SYSTEMS;

EID: 33645232695     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2006.49     Document Type: Article

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