Interfacing a high speed crypto accelerator to an embedded CPU

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2004, Pages 488-492

  Hodjat, Alireza ^a   Verbauwhede, Ingrid ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY COSTS; HIGH SPEED CRYPTO ACCELERATOR; LOOK UP TABLES; MEMORY-MAPPED INTERFACE;

COMPUTER SOFTWARE; COST ACCOUNTING; ENERGY UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS;

CRYPTOGRAPHY;

EID: 21644488432     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. LEON SPARC V8 CPU Core, Gaisler Research, http://www.gaisler.com/
2. Federal Information Processing Standards (FIPS), Publication 197, "Advanced Encryption Standard" November 2001, available at: http://csrc.nist.gov/publications/fips/fips197/fips197.pdf.
3. http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title= Platform+FPG As
4. http://www.insight-electronics.com/Memec/iplanet/linkl/VIRTEX11MBV1000. PDF
5. F. Barat, R. Lauwereins, G. Deconinck, "Reconfigurable Instruction Set Processors from a HW/SW Prospective", IEEE Transactions on Software Engineering, Vol. 28, No. 9, September 2002.
6. S. Ravi, A. Raghunathan, Potlapally, Sankaradass, "System design methodologies for a wireless security processing platform", DAC 2002, New Orleans, USA.
7. Xtensa application specific microprocessor solutions - Overview handbook. Tensilica Inc., 2001.
8. Alireza Hodjat, Ingrid Verbauwhede, "High-Throughput Programmable Cryptocoprocessor", IEEE Micro Magazine, Volume: 24, Issue: 3, Pages: 34-45, May/June 2004.