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Volumn 30, Issue 3, 2009, Pages 231-233

Degradation mechanism of Poly-Si TFTs dynamically operated in OFF region

Author keywords

AC stress; Dynamic stress; Poly Si thin film transistors (TFTs); Reliability

Indexed keywords

CIRCUIT THEORY; DEGRADATION; DROPS; POLYSILICON; RELIABILITY; SEMICONDUCTING ORGANIC COMPOUNDS; THIN FILM DEVICES; VOLTAGE CONTROL;

EID: 62649151339     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2010784     Document Type: Article
Times cited : (18)

References (7)
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    • Y.-H. Tai, C. C. Pai, B. T. Chen, and H. C. Cheng, "A source-follower type analog buffer using poly-Si TFTs with large design windows," IEEE Electron Device Lett., vol. 26, no. 11, pp. 811-813, Nov. 2005.
    • (2005) IEEE Electron Device Lett , vol.26 , Issue.11 , pp. 811-813
    • Tai, Y.-H.1    Pai, C.C.2    Chen, B.T.3    Cheng, H.C.4
  • 2
    • 0035471242 scopus 로고    scopus 로고
    • Reliability of low temperature poly-silicon TFTs under inverter operation
    • Oct
    • Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura, and Y. Tsuchihashi, "Reliability of low temperature poly-silicon TFTs under inverter operation," IEEE Trans. Electron Devices, vol. 48, no. 10, pp. 2370-2374, Oct. 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , Issue.10 , pp. 2370-2374
    • Uraoka, Y.1    Hatayama, T.2    Fuyuki, T.3    Kawamura, T.4    Tsuchihashi, Y.5
  • 3
    • 0034482025 scopus 로고    scopus 로고
    • Reliability of high-frequency operation of low-temperature polysilicon thin film transistors under dynamic stress
    • Dec
    • Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura, and Y. Tsuchihashi, "Reliability of high-frequency operation of low-temperature polysilicon thin film transistors under dynamic stress," Jpn. J. Appl. Phys., vol. 39, no. 12A, pt. 2, pp. L1209-L1212, Dec. 2000.
    • (2000) Jpn. J. Appl. Phys , vol.39 A , Issue.12 PART. 2
    • Uraoka, Y.1    Hatayama, T.2    Fuyuki, T.3    Kawamura, T.4    Tsuchihashi, Y.5
  • 4
    • 33947244303 scopus 로고    scopus 로고
    • Analysis of poly-Si TFT degradation under gate pulse stress using the slicing model
    • Dec
    • Y.-H. Tai, S.-C. Huang, and C.-K. Chen, "Analysis of poly-Si TFT degradation under gate pulse stress using the slicing model," IEEE Electron Device Lett., vol. 27, no. 12, pp. 981-983, Dec. 2006.
    • (2006) IEEE Electron Device Lett , vol.27 , Issue.12 , pp. 981-983
    • Tai, Y.-H.1    Huang, S.-C.2    Chen, C.-K.3
  • 6
    • 34249899101 scopus 로고    scopus 로고
    • Degradation of the capacitance-voltage behaviors of the low-temperature polysilicon TFTs under DC stress
    • Y.-H. Tai, S.-C. Huang, C. W. Lin, and H. L. Chiu, "Degradation of the capacitance-voltage behaviors of the low-temperature polysilicon TFTs under DC stress," J. Electrochem. Soc., vol. 154, no. 7, pp. 611-618, 2007.
    • (2007) J. Electrochem. Soc , vol.154 , Issue.7 , pp. 611-618
    • Tai, Y.-H.1    Huang, S.-C.2    Lin, C.W.3    Chiu, H.L.4
  • 7
    • 56049094369 scopus 로고    scopus 로고
    • Estimation ofthe effect of channel shortening for P-type poly-Si TFTs under AC stress
    • S.-C. Huang, H.-C. Tsao, and Y.-H. Tai, "Estimation ofthe effect of channel shortening for P-type poly-Si TFTs under AC stress," in Proc. IDMC, 2007, pp. 134-137.
    • (2007) Proc. IDMC , pp. 134-137
    • Huang, S.-C.1    Tsao, H.-C.2    Tai, Y.-H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.