Reliability of low temperature poly-silicon TFTs under inverter operation

IEEE Transactions on Electron Devices

Volumn 48, Issue 10, 2001, Pages 2370-2374

  Uraoka, Yukiharu ^a   Hatayama, Tomoaki ^a   Fuyuki, Takashi ^a   Kawamura, Tetsuya ^b   Tsuchihashi, Yuji ^b  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b PANASONIC CORPORATION   (Japan)

Author keywords

Grain boundary; Hot carriers; Photon emission; Polycrystalline silicon thin film transistor (poly Si TFT); Reliability

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; ELECTRON EMISSION; ELECTRON TRANSPORT PROPERTIES; GRAIN BOUNDARIES; HOT CARRIERS; LOW TEMPERATURE PROPERTIES; MATHEMATICAL MODELS; MICROSCOPIC EXAMINATION; POLYSILICON; RELIABILITY;

DYNAMIC BIAS STRESS; EMISSION MICROSCOPY; PHOTON EMISSION;

THIN FILM TRANSISTORS;

EID: 0035471242     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.954479     Document Type: Article

References (10)

1. A 2.8-in. diagonal low-temperature-purcessed poly-Si TFT with a new LDD structure
2. New degradation phenomenon in wide channel poly-Si TFT's fabricated by low temperature process
3. Hot-carrier effects and gate currents of low-temperature poly-Si TFT's for liquid crystal displays
4. Investigation of the relationship between hot-carrier degradation and kink effect in low-temperature poly-Si TFTs
5. Reliability of low temperature poly-silicon TFT's under dynamic stress
6. Reliability evaluation method of low temperature poly-silicon TFT's under dynamic stress
7. Hot carrier effect in low temperature poly-silicon thin film transistors
8. Hot carrier evaluation of MOSFET's in ULSI circuit using photon emission method
9. Hot-electron and hole-emission effects in short n-channel MOSFET's
10. Analysis of hot carrier effects in low temperature poly-Si TFT's using device simulator