Double-patterning decomposition, design compliance, and verification algorithms at 32nm hp

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7122, Issue , 2008, Pages

  Tritchkov, Alexander ^a   Glotov, Petr ^a   Komirenko, Sergiy ^a   Sahouria, Emile ^a   Torres, Andres ^a   Seoud, Ahmed ^a   Wiaux, Vincent ^a,b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b IMEC   (Belgium)

Author keywords

Design compliance; Design verification; Double patterning; OPC; Pitch splitting

Indexed keywords

CHIP DESIGNS; CRITICAL LAYERS; DESIGN VERIFICATION; DOUBLE PATTERNING; HIGH CAPACITIES; IC DESIGNS; MANUFACTURING KNOWLEDGE; MASK SYNTHESIS; MENTOR GRAPHICS; MULTIPLE EXPOSURES; OPC; PARAMETERIZATION SCHEMES; PATTERNING TECHNOLOGIES; PHYSICAL EFFECTS; PHYSICAL SYNTHESIS; PITCH SPLITTING; PROCESS VARIANCES; RAYLEIGH LIMITS; RESIST LAYERS; SUB RESOLUTIONS; TECHNOLOGY STRATEGIES; VERIFICATION ALGORITHMS;

DYNAMIC POSITIONING; INDUSTRIAL APPLICATIONS; INTEGRATED CIRCUITS; OPTOELECTRONIC DEVICES; PERCOLATION (SOLID STATE); TECHNOLOGY;

DESIGN;

EID: 62649143646     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.801381     Document Type: Conference Paper

References (6)

1. Mireille Maenhoudt et al., "Double Patterning Scheme for Sub-0.25 kl Single Damascene Structure at NA=0.75, λ=193nm", Proceeding of SPIE Vol. 5754, (2006).
2. Lars Liebmann et al., "Layout Methodology Impact of Resolution Enhancement Technique", Electronic Design Process, Monterey, CA, (2003).
3. Mireille Maenhoudt et al. "Alternative process schemes for double patterning that eliminate the intermediate etch step," Proceedings of SPIE Vol. 6924, (2008).
4. Vincent Wiaux et al., "Split and Design Guidelines for Double patterning," Proceedings of SPIE Vol. 6924, (2008).
5. Janko Versluijs et al., "30nm half-pitch metal patterning using Motif™ CD shrink technique and double patterning", Proceedings of SPIE Vol. 6924, (2008).
6. G. Bailey, A. Tritchkov, L. Hong., J. Park, V. Wiaux, E. Hendrickx, S. Verhaegen, P. Xie, J. Versluijs, "Double pattern EDA solutions for 32nm HP and beyond", Proceedings of SPIE Vol. 6521, (2007).