Implementing FFT-based digital channelized receivers on FPGA platforms

IEEE Transactions on Aerospace and Electronic Systems

Volumn 44, Issue 4, 2008, Pages 1567-1585

  Sánchez, Miguel A ^a   Garrido, Mario ^a   Lopez Vallejo, Marisa ^a   Grajal, Jesús ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

Computer architecture; Field programmable gate arrays; Real time systems; Receivers; Signal processing; Throughput; Wideband

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTERS; FAST FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTERACTIVE COMPUTER SYSTEMS; LOGIC GATES; RADIO RECEIVERS; SIGNAL PROCESSING; TELECOMMUNICATION SYSTEMS;

BIT WIDTHS; DIGITAL CHANNELIZED RECEIVERS; DIGITAL RECEIVERS; FEEDFORWARD; FFT ALGORITHMS; FIELD-PROGRAMMABLE GATE ARRAYS; HARDWARE IMPLEMENTATIONS; IN-DEPTH STUDIES; KEY DESIGN PARAMETERS; MAXIMIZE THROUGHPUTS; PIPELINED ARCHITECTURES; REAL-TIME PERFORMANCE; RECEIVERS; SIGNAL PROCESSING SYSTEMS; WIDEBAND;

REAL TIME SYSTEMS;

EID: 62349094472     PISSN: 00189251     EISSN: None     Source Type: Journal    
DOI: 10.1109/TAES.2008.4667732     Document Type: Article

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