High-performance FFT processing using reconfigurable logic

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2001, Pages 1353-1356

  Szedo, Gabor ^a   Yang, Vanessa ^a   Dick, Chris ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; DIGITAL STORAGE; FAST FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DEVICES;

DISTRIBUTED BLOCK MEMORY; PARALLEL MULTIPLIER; RECONFIGURABLE LOGIC;

DIGITAL SIGNAL PROCESSING;

EID: 0035573377     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/acssc.2001.987712     Document Type: Conference Paper

References (4)

1. An algorithm for the machine computation of complex fourier series
2. A simple fixed-point error bound for the fast fourier transform