Rapid prototyping design acceleration using a novel merging methodology for partial configuration streams of Xilinx Virtex-II FPGAs

Proceedings of the International Workshop on Rapid System Prototyping

Volumn 2006, Issue , 2006, Pages 193-199

  Bieser, C ^a   Mueller Glaser, K D ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATION; COMPUTER AIDED DESIGN; FIELD PROGRAMMABLE GATE ARRAYS; RANDOM ACCESS STORAGE; SOFTWARE ENGINEERING;

DESIGN SUPPORT; ELECTRONIC DESIGNS; RAM-BASED FPGA; VHDL OR VERILOG;

RAPID PROTOTYPING;

EID: 33751416365     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RSP.2006.32     Document Type: Conference Paper

References (20)

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