Dynamic Data Stability in Low-power SRAM Design

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 237-240

  Sharifkhani, M ^a   Jahinuzzaman, S M ^a   Sachdev, M ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; INTEGRATED CIRCUITS; LOGIC DESIGN; STABILITY; STABILITY CRITERIA; STATIC RANDOM ACCESS STORAGE;

CRITERIA OF STABILITY; DATA STABILITIES; DYNAMIC BEHAVIORS; DYNAMIC ENVIRONMENTS; DYNAMIC POWER CONSUMPTION; OPERATING VOLTAGE; SRAM CELL STABILITY; WRITE OPERATIONS;

INTEGRATED CIRCUIT DESIGN;

EID: 59349089392     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405722     Document Type: Conference Paper

References (9)

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3. M. Sharifkhani and M. Sachdev, "A low power SRAM architecture based on segmented virtual grounding, " Proceedigs of IEEE Symposium on Low-Power Electronics and Design (ISLPED), 256-261, Oct. 2006.
4. M. Khellah et al., "Wordline and bitline pulsing schemes for improving SRAM cell stability in low-vcc 65nm CMOS designs, " IEEE Symp. on VLSI Circuits Digest of Tech. Papers, pp. 9-10, 2006.
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7. M. Sharifkhani, M. Sachdev, "Segmented virtual ground architecture for low-power embedded SRAM, " IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, pp. 196-205, Feb. 2007.
8. N. Verma and A. Chandrakasan, "A 65nm 8T sub-Vt SRAM employing sense-amplifier redundancy, " IEEE ISSCC Digest of Tech. Papers, pp. 328-329, Feb. 2007.
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