Dynamic data stability in sram cells and its implications on data stability tests

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn 2006, Issue , 2006, Pages 7-13

  Sharifkhani, M ^a   Jahinuzzaman, S M ^a   Sachdev, M ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA REDUCTION; DYNAMIC PROGRAMMING; FAULT TOLERANT COMPUTER SYSTEMS; SET THEORY;

DATA STABILITY; HAMMER TESTS; SRAM CELLS;

STATIC RANDOM ACCESS STORAGE;

EID: 34047234996     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2006.12     Document Type: Conference Paper

References (13)

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