Performance improvement of flash memory using AlN as charge-trapping Layer

Microelectronic Engineering

Volumn 86, Issue 3, 2009, Pages 299-302

  Chakraborty, P ^a   Mahato, S S ^a   Maiti, T K ^a   Bera, M K ^a   Mahata, C ^a   Samanta, S K ^b   Biswas, A ^c   Maiti, C K ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

^b CYPRESS SEMICONDUCTOR   (United States)

^c JADAVPUR UNIVERSITY   (India)

Author keywords

AlN; High k dielectric; Pulse; Threshold voltage shift

Indexed keywords

CHARGE TRAPPING; DATA STORAGE EQUIPMENT; DIELECTRIC FILMS; DIELECTRIC MATERIALS; GERMANIUM; NITRIDES; OXIDE FILMS; POLYSILICON; SEMICONDUCTOR STORAGE; SILICON COMPOUNDS; THRESHOLD VOLTAGE;

AGGRESSIVE SCALING; ALN; ALN FILMS; CHARGE LOSS; CHARGE STORAGES; DEVICE APPLICATIONS; GATE BIAS VOLTAGES; HIGH-K DIELECTRIC; HIGH-K DIELECTRIC FILMS; MEMORY STRUCTURES; NANOCRYSTAL MEMORIES; NON UNIFORMITIES; NON-VOLATILE MEMORIES; OPERATING VOLTAGES; PERFORMANCE IMPROVEMENTS; POLY SILICONS; POLYSILICON OXIDE NITRIDE OXIDE SILICONS; PROGRAM/ERASE; PULSE; PULSE WIDTHS; THRESHOLD VOLTAGE SHIFT; TUNNEL DIELECTRICS;

FLASH MEMORY;

EID: 59049093079     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2008.10.008     Document Type: Article

References (15)

1. Flash memory market to pass 20 billion dollars by 2010, Vnunet.com.
2. Tiwari S., Rana F., Hanafi H., Hartstein A., Crabbe E.F., and Chan K. Appl. Phys. Lett. 68 10 (1996) 1377-1379
3. Wang S., Liu W., Wan Q., Dai J.Y., Lee P.F., Suhua L., Shen Q., Zhang M., Song Z., and Lin C. Appl. Phys. Lett. 86 11 (2005) 113105-113107
4. Samanta S.K., Singh P.K., Yoo W.J., Samudra G., Yeo Y.C., Bera L.K., and Balasubramanian N. IEDM Tec. Dig. (2005) 170-173
5. Lee J.J., and Kwong D.L. IEEE Trans. 52 (2005) 507-511
6. J. Bu, M.H. White, Retention reliability enhanced SONOS NVSM with scaled programming voltage, in: Proc. IEEE Aerospace Conf., vol. 5, 2002, pp. 2383-2390.
7. M. She, H. Takeuchi, T.-J. King, Improved SONOS-type flash memory using HfO as trapping layer, in: Proc. IEEE Nonvolatile Semiconductor Memory Workshop, vol. 33, 2003, pp. 53-55.
8. Sugizaki T., Kohayashi M., Ishidao M., Minakata H., Yamaguchi M., Tamura Y., Sugiyama Y., Nakanishi T., and Tanaka H. Symp. on VLSI Tech. Dig. (2003) 27
9. Tan Y.N., Chim W.K., Choi W.K., Joo M.S., Ng T.H., and Cho B.J. IEDM Tech. Dig. 20 (2004) 889-892
10. Spechta M., Reisingerb H., Hofmanna F., Schulza T., Landgrafa E., Luykena R.J., Rösnera W., Griebc M., and Risch L. Solid-State Electron. 49 (2005) 716-720
11. Lee C.H., Hur S.H., Shin Y.C., Choi J.H., Park D.G., and Kim K. Appl. Phys. Lett. 86 (2005) 152908-152910
12. Laia C.H., China A., Kaoa H.L., Chena K.M., Hongb M., Kwoc J., and Chic C.C. Symp. on VLSI Tech. Dig. (2006) 44-45
13. Murphy E.L., and Good Jr. R.H. Phys. Rev. 102 6 (1956) 1464
14. Bu J., and White M.H. Solid-State Electron. (2001) 45-47
15. French M.L., and White M.H. Solid State Electron 37 (1994) 1913-1923